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Sunday Night at DAC

Sunday Night at DAC
by Daniel Payne on 06-05-2011 at 7:23 pm

San Diego Arrival
It’s another picture perfect day in San Diego as I arrived and checked into the Hyatt. The view from the 40th floor looked magnificent, with the Convention Center just a few minutes away in the distance:

Registration

Check in at DAC is quite automated and it took only a minute to receive my official badge with… Read More


ARM vs Intel step 2…Intel’s nervous breakdown about Microsoft… and cut ATOM price

ARM vs Intel step 2…Intel’s nervous breakdown about Microsoft… and cut ATOM price
by Eric Esteve on 06-01-2011 at 8:52 am

In the unspoken war between ARM and Intel, a couple of interesting facts have surfaced during the last few days:

  • Intel nervous breakdown in respect with their 30 years old accomplice in the Wintel gang
  • ATOM latest version Cedar Trail fabbed on 32nm technology, targeted for mobile computing, will be priced at a 30% to 50% discount…
Read More

65nm to 45nm SerDes IP Migration Success Story

65nm to 45nm SerDes IP Migration Success Story
by Daniel Nenni on 05-25-2011 at 3:43 pm

The problem:To move a single lane variable data rate SerDes (serializer-deserializer) from a 65nm process to a 45nm process, achieving a maximum performance of up to 10.3 Gbps. This is a large piece of complex mixed-signal IP with handcrafted analog circuits. Circuit performance and robustness are critical and must be maintainedRead More


FPGA Prototypes Made Easy

FPGA Prototypes Made Easy
by Paul McLellan on 05-23-2011 at 5:00 am

FPGA-based prototype boards are a fast, cost-effective platform for SoC system validation but they are notoriously difficult to set up and to debug. There is a big upside, however, allowing early software integration and testing and thus finding bugs in both the software and the SoC earlier. This approach is much cheaper than … Read More


Right-source your electronic designs

Right-source your electronic designs
by nitindeo on 05-19-2011 at 5:42 pm

Concept2Silicon Systems (C2SiS) is focused on providing complete solutions for complex SoC and System designs with best in class engineering capabilities and most cost-efficient business model. Our highly capable engineering team has experience in delivering 200+ silicon and system design solutions to its customers in Read More


Adjusting Custom IP to Process Changes

Adjusting Custom IP to Process Changes
by Daniel Nenni on 05-16-2011 at 1:57 pm

A High-Definition Multimedia Interface (HDMI) IP core was being implemented in an advanced process technology. This fairly large and complex analog mixed-signal (AMS) IP comprising over 130K devices was close to being finalized and shipped to the customer. But many design rules at the foundry were unexpectedly changed fromRead More


How Good is Your Verification?

How Good is Your Verification?
by Paul McLellan on 05-11-2011 at 5:00 am

The traditional way for analyzing the effectiveness of testing in the software world and in the RTL world is code coverage. Make sure that every line of code is executed. This is a pretty crude measure since even 100% code coverage doesn’t mean that all the condition has really been tested but it is certainly necessary–after… Read More


40nm to 28nm Migration Success Story

40nm to 28nm Migration Success Story
by Paul McLellan on 05-08-2011 at 4:00 pm

The problem:To move dual-port SRAM library and macros from a 40nm process to a 28nm process. In addition to all the changes between two different foundry processes, the 28nm rules are disruptive and incompatible with the previous rules. The memory corecells (foundry-specific) would also need to be completely replaced.

Current… Read More


Thanks for the memory

Thanks for the memory
by Paul McLellan on 04-20-2011 at 1:26 am

One of the most demanding areas of layout design has always been memories. Whereas digital design often uses somewhat simplified design rules, memories have to be designed pushing every rule to the limit. Obviously even a tiny improvement in the size of a bit cell multiplies up into significant area savings when there are billions… Read More


DDR4 Controller IP, Cadence IP strategy… and Synopsys

DDR4 Controller IP, Cadence IP strategy… and Synopsys
by Eric Esteve on 04-14-2011 at 4:17 am


I will share with you some strategic information released by Cadence last week about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their closestRead More