image ad mdx hip webinar automating integration workflow 800x100 (1)
WP_Term Object
(
    [term_id] => 1
    [name] => Uncategorized
    [slug] => uncategorized
    [term_group] => 0
    [term_taxonomy_id] => 1
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 186
    [filter] => raw
    [cat_ID] => 1
    [category_count] => 186
    [category_description] => 
    [cat_name] => Uncategorized
    [category_nicename] => uncategorized
    [category_parent] => 0
    [is_post] => 
)

One Trillion Transistor IC Layout at DAC

One Trillion Transistor IC Layout at DAC
by Daniel Payne on 06-17-2011 at 4:20 pm

Intro
Micro Magic was the only company at DAC that showed an IC layout editor with 1 Trillion transistors loaded in it, wow.


Karen Mangum

Notes
I chatted with Katherine Hays, a 12 year veteran of Micro Magic about what was new at DAC this year.

Max-3D – Can handle stacked wafers with TSV
– Gary Smith’s list of must-see for 3D
–… Read More


Berkeley Design Automation at DAC

Berkeley Design Automation at DAC
by Daniel Payne on 06-17-2011 at 4:01 pm

Intro
Simon Young, Product Marketing manager at BDA gave me an update at DAC last week on their circuit simulator, Analog Fast SPICE (AFS).

Notes

Quarterly release: 2011 Q2 now

Speed Improvements: Still 5 to 10X speed improvement over other SPICE tools

Multi-Threading – 2 to 4 X improvement using 4 to 8 cores.

Device Noise – three … Read More


Extreme DA at DAC

Extreme DA at DAC
by Daniel Payne on 06-14-2011 at 3:01 pm

Intro
Over the lunch hour on Tuesday at DAC I met with Emre Tuncer, VP – Product Engineering & Applications and heard about extraction and timing analysis.

Notes

GoldX – parasitic extractor. Fast extractor, recently announced, all new technology, early customer adoption. One customer deploying it in 40nm, soon to be 28nm.… Read More


Blue Pearl at DAC

Blue Pearl at DAC
by Daniel Payne on 06-14-2011 at 1:03 pm

Intro
It’s all about analyzing RTL and creating timing constraints at Blue Pearl, so I stopped by their booth on Tuesday morning to get an update on what’s new for 2011.

Notes

What’s New in 2011 at Blue Pearl Software

New designer experience, ease of use. Brand new GUI.

Work with RTL to synthesis tools to get best timingRead More


Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 2 of 2)

Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 2 of 2)
by Daniel Payne on 06-14-2011 at 12:43 pm

Dipesh Patel, VP Engineering, ARM Physical IP

Consumer demand for smart devices, short life cycles (SmartPhone, Tablets, Internet screens)

Processor speeds: 1GHz to 1.5GHz
SOC Memory: 600MHz to 1.2 GHz
How power efficient?
How is the layout density?

Standard Cells: multi-channel, multi-vt (4) libraries

Memory Compilers:Read More


Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 1 of 2)

Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 1 of 2)
by Daniel Payne on 06-14-2011 at 12:26 pm

Intro
The 28nm nodes is ready with foundry silicon, IP and EDA tools. Tuesday morning at the DAC breakfast I learned more about the 28nm eco-system.

Notes
Why 32/28nm
Lower power, high integration requirements, mobile applications

What is Ready?
IP is qualified (ARM, Memories, Foundation IP, SNPS IP, PDKs)
Read More


CyberEDA adds a Transistor-Level Debugger

CyberEDA adds a Transistor-Level Debugger
by Daniel Payne on 06-13-2011 at 6:34 pm

Intro
I met with CK Lee, founder of Cyber EDA at his booth on Monday evening in San Diego. Last year I learned about their new SPICE circuit simulator named PCSIM, this year the new product is called ADDS-Debugger.



Notes

2010 – Announced a debugger

2011 ADDS Debugger – trace at the transistor level your design
– Signal tracing… Read More


QuickCap for IC Extraction at DAC 2011

QuickCap for IC Extraction at DAC 2011
by Daniel Payne on 06-13-2011 at 6:08 pm

Intro
John and Ralph from Magma gave me an update on QuickCap at DAC on Monday afternoon in their demo suite.

Notes
John Schritz – Sr AE
Ralph Iverson, Ph. D. (wrote QuickCap)

John Schritz
– Digital Signoff, extraction
– QCP: 2.5D RC for full ASIC designs
– QuickCAP NX: 3D field solver
– QCP:

Demo – 1.5 million… Read More


FineSIM adds RF Analysis plus new Tcl Circuit Checks

FineSIM adds RF Analysis plus new Tcl Circuit Checks
by Daniel Payne on 06-13-2011 at 4:58 pm

At DAC I spent time in the Magma FineSIM demo suite on Monday morning.

Greg Curtis – Product Director, Custom Design Business Unit

– Talus for Digital Design
– FineSim does: SPICE, FastSPICE, Characterization
– Flows Demoed at DAC: High Performance Core, SOC, ASIC/ASSP, AMS, Memory
– What’s New in FineSim?o… Read More


The Secret of Analog Design

The Secret of Analog Design
by Paul McLellan on 06-09-2011 at 5:15 pm

Everybody knows that digital designers run on pizza and soda, what one might describe as poor food and weak drinks. At DAC in San Diego I discovered a restaurant that gave away the secret to analog design. And you thought it was a good layout editor and a good circuit simulator. But it turns out that the secret to analog is good food and… Read More