Dipesh Patel, VP Engineering, ARM Physical IP
Consumer demand for smart devices, short life cycles (SmartPhone, Tablets, Internet screens)
Processor speeds: 1GHz to 1.5GHz
SOC Memory: 600MHz to 1.2 GHz
How power efficient?
How is the layout density?
Standard Cells: multi-channel, multi-vt (4) libraries
Memory Compilers: single port, multi port, ROM
7 families to choose from
28nm libraries nominal VDD of 1.0V
Processor Optimization Package (POP)
–Reference flow, documentation, guidelines
–ARM certified benchmarking
Cortex A9 – 1.3GHz performance now
Silicon Validated – created Test Chips for GLOBALFOUNDRIES and Samsung at 32nm and 28nm nodes
Fab Synch – migrate any design from one fab to another one
Ready to Start – http://designstart.arm.com/
Andy Potemski – Director of Global Technical Services, Synopsys
Lynx Design System – About 2 years old, design system of silicon realization tools
–Off the shelf productivity
–A core flow for building an ARM Cortex A9
–Configure Flow with High Performance Libraries and IP
o Use DesignWare or 3[SUP]rd[/SUP] party IP
–Optimize the methodology for design specific needs
–Optimize the design floor plan in the context of the full chip
o Quad core A9 floor plan
o Explore and optimize
–Optimize performance and power
o Detailed routing
o Trend analysis of design metrics like power, area, speed
–Optimize the design flow turn around time
o Track execution of all tools
o Analyze the profile of each tool
o Identify tool bottlenecks
Q: The ARM brochure says up to 25% higher performance or 80% less power. Can I get both?
A: That’s very difficult. It’s really a tradeoff that you have to choose between.
Q: How will work on 28nm help 20nm, especially in light of litho effects?
A: We’re collaborating early in the development of 20nm to learn from our Common Platform partners. Double patterning is needed for 20nm. Expect to see a 50% improvement in density going from 28nm to 20nm node. Computational lithography required on 20nm. Another level of litho complexity make architectural exploration a challenge. Trying to minimize the number of double patterning layers required.
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