At ISSCC this year Samsung published a paper entitled “A 10nm FinFET 128Mb SRAM with Assist Adjustment System for Power, Performance, and Area Optimization. In the paper Samsung disclosed a high density 6T SRAM cell size of 0.040µm[SUP]2[/SUP]. I thought it would be interesting to take a look at how this cell size stacks … Read More
Good bye and thank you, Andy Grove!
You are gone. And with you, gone is one of the greatest leaders of our times.
In the coming days many voices will speak about the ways in which you touched countless lives, inspired a generation of engineers to create and fuel the digital revolution, and demonstrated your own brand of leadership traits in pursuit of excellence. My … Read More
Intel Adds ‘Authenticate’ Multi-Factor Security Feature
Last summer, Intel launched their 14nm, 6th Generation Core processors, code-named ‘Skylake’, alongside Microsoft’s new Windows 10 operating system. As things usually go in the enterprise world, the commercial 6th Generation of Intel’s Core vPro processors weren’t too far behind with increased security and manageability… Read More
Intel EUV Photoresist Progress and ASML High NA EUV
SPIE Days 3 and 4:
Anna Lio of Intel presented EUV resists: What’s next?
Intel wants to insert EUV at 7nm but it has to be ready and economical. Critical Dimension Uniformity (CDU), Line Width Roughness (LWR) and edge placement/stochastics are all stable on 22nm, 14nm and 10nm pilot lines.… Read More
TSMC and Intel on the Long Road to EUV
Today is the first day of the SPIE Advanced Lithography Conference and Extreme Ultraviolet (EUV) updates were a big focus.… Read More
Inception of "Intel Inside"
Let me start with a quote:
“Competition is always a good thing. It forces us to do our best. A monopoly renders people complacent and satisfied with mediocrity.”– Nancy Pearcy
By the end of post, it will be quite evident that it was the competition that led to one of the classiest campaign “Intel Inside” for its processors. As I mentioned… Read More
Intel to Focus on IoT and NOT Mobile?
The Intel Q4 investor call was last week and as Brian Krzanich approaches his 3[SUP]rd[/SUP] year as Intel CEO a new synergistic corporate strategy is emerging:
That strategy is also resulting in the evolution of our business model to focus on three key areas of growth: The Data Center, the Internet of Things, and Memory.
DCG, IoTG… Read More
Intel reaches for all-new experience at CES2016
When Gary Shapiro introduced Brian Krzanich for Intel’s keynote at #CES2016, he just possibly may have been the last person to say “Moore’s Law” outside of a museum ever again. Krzanich was about to take Intel into new territory, where “Copy Exactly” and tick-tock also don’t matter.… Read More
IEDM Blogs – Part 5 – Intel and Micron 3D NAND
At IEDM Intel and Micron presented “A Floating Gate Based 3D NAND Technology With CMOS Under Array” authored by Krishna Parat and Chuck Dennison.
As I previously discussed in my blog on the IEDM memory short course and blog on IMEC’s work on high mobility 3D NAND channels, continuing to scale 2D Flash has become extremely difficult… Read More
Samsung Versus Intel at 14nm
Daniel Nenni recently blogged about Intel’s claims of industry leading process density that were made at their analysts meeting. It isn’t clear to me why Intel makes this such a big focus at the analysts meetings, they really don’t compete with the foundries much but this seems to be a big deal to them. I thought it would be interesting… Read More