WP_Term Object
(
    [term_id] => 14
    [name] => Synopsys
    [slug] => synopsys
    [term_group] => 0
    [term_taxonomy_id] => 14
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 705
    [filter] => raw
    [cat_ID] => 14
    [category_count] => 705
    [category_description] => 
    [cat_name] => Synopsys
    [category_nicename] => synopsys
    [category_parent] => 157
    [is_post] => 
)
SNPS1555030139 snug sv 2025 semiwiki ad 800x100px 
WP_Term Object
(
    [term_id] => 14
    [name] => Synopsys
    [slug] => synopsys
    [term_group] => 0
    [term_taxonomy_id] => 14
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 705
    [filter] => raw
    [cat_ID] => 14
    [category_count] => 705
    [category_description] => 
    [cat_name] => Synopsys
    [category_nicename] => synopsys
    [category_parent] => 157
    [is_post] => 
)
Synopsys
Posted on

Multiprotocol 10G-KR and PCIe Gen-3 PHY IP will support big data and smartphone explosion

Multiprotocol 10G-KR and PCIe Gen-3 PHY IP will support big data and smartphone explosion
by Eric Esteve on 03-07-2013 at 7:47 am
Categories: IP, Synopsys

We have frequently said in Semiwiki how crucial is it for the SC industry to benefit from high quality PHY IP… even if, from a pure business point of view (MBA minded), PHY IP business does not look so attractive. In fact, to be able to design on-the-edge SerDes and PLL (the two key pieces), you need to build and maintain a highly skilled… Read More

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Modeling TSV, IBIS-AMI and SERDES with HSPICE

Modeling TSV, IBIS-AMI and SERDES with HSPICE
by Daniel Payne on 02-21-2013 at 8:10 pm
Categories: EDA, IP, Synopsys

The HSPICE circuit simulator has been around for decades and is widely used by IC designers worldwide, so I watched the HSPICE SIG by video today and summarize what happened. Engineers from Micron, Altera and AMD presented on how they are using HSPICE to model TSVs, IBiS-AMI models and SERDES, respectively.… Read More

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Developing ARM v8 Code…Today

Developing ARM v8 Code…Today
by Paul McLellan on 02-13-2013 at 12:50 pm
Categories: Arm, EDA, IP, Synopsys

You are going to be developing software for an SoC that contains an ARM Cortex-A57 64-bit CPU. Or perhaps it is an SoC containing ARM’s hybrid big.LITTLE multi-core architecture that combines one or more low power cores with some high power, high performance cores to get the best of both worlds: high throughput when it is needed… Read More

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Help, my IP has fallen and can’t get up

Help, my IP has fallen and can’t get up
by Don Dingee on 02-03-2013 at 8:10 pm
Categories: EDA, FPGA, IP, Synopsys

We’ve been talking about the different technologies for FPGA-based SoC prototyping a lot here in SemiWiki. On the surface, the recent stories all start off pretty much the same: big box, Xilinx Virtex-7, wanna go fast and see more of what’s going on in the design. This is not another one of those stories. I recently sat down with Mick… Read More

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New PCI Express 3.0 Equalization Requirements

New PCI Express 3.0 Equalization Requirements
by Eric Esteve on 01-22-2013 at 9:18 am
Categories: IP, Synopsys

PCI Express 3.0 increased the supported data rate to 8 Gbps, which effectively doubles the data rate supported by PCI Express 2.0. While the data rate was increased, no improvement was made to the channels. As such, an 8 Gbps channel in PCIe 3.0 experiences significantly more loss than one implemented in PCIe 2.0. To compensate for… Read More

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IP vendors enable SuperSpeed USB IP take off in 2012

IP vendors enable SuperSpeed USB IP take off in 2012
by Eric Esteve on 01-15-2013 at 5:09 am
Categories: IP, Synopsys

SuperSpeed USB has been clearly ranked in the Interface protocols winner list, see this previous post. It could be interesting to dig into this IP market segment, determine in which applications USB 3.0 has been successfully deployed and who are the IP vendors serving this market, enabling SuperSpeed USB to take off.

SuperSpeed… Read More

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A Brief History of Synopsys DesignWare ® IP

A Brief History of Synopsys DesignWare ® IP
by Daniel Nenni on 01-11-2013 at 9:00 am
Categories: IP, Synopsys

Let’s play word association. I say “EDA”, you immediately think “Synopsys”. I say “IP” and although 15 years ago you may not, today, you think “Synopsys”. For nearly two decades, Synopsys has grown its IP business through both organic development and acquisition, with a clear focus on enabling designers to meet their time-to-market… Read More

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How much SRAM proportion could be integrated in SoC at 20 nm and below?

How much SRAM proportion could be integrated in SoC at 20 nm and below?
by Eric Esteve on 11-20-2012 at 4:45 am
Categories: IP, Synopsys

Once upon a time, ASIC designers were integrating memories in their design (using a memory compiler being part of the design tools provided by the ASIC vendor), then they had to make the memory observable, controllable… and start developing the test program for the function, not a very enthusiastic task (“AAAA” and “5555” and other… Read More

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IP Wanna Go Fast, Core Wanna Not Rollover

IP Wanna Go Fast, Core Wanna Not Rollover
by Don Dingee on 08-23-2012 at 8:15 pm
Categories: EDA, IP, Synopsys
2 Comments

At a dinner table a couple years ago, someone quietly shared their biggest worry in EDA. Not 2GHz, or quad core. Not 20nm, or 450mm. Not power, or timing closure. Call it The Rollover. It’s turned out to be the right worry.

Best brains spent inordinate hours designing and verifying a big, hairy, heavy breathing processor core to do … Read More