As the size and complexity of System On Chip design has rapidly expanded in recent years, the need to use cache memory to improve throughput and reduce power has increased as well. Originally, cache memory was used to prevent what was then a single processor from making expensive off chip access for program or data memory. With the… Read More
Arteris Unveils Solution for Heterogeneous Cache Coherent SOC’s
Designing SOC’s for markets like automotive and mobile electronics requires taking advantage of every opportunity for optimization. One way to do this is through building a cache coherent system to boost speed and reduce power. Recently, NXP decided to go about this on their automotive MCU based SOC’s by using Arteris’ just-announced… Read More
Cache Coherent Systems Get a Boost from New Technology
The speed and power penalties for accessing system RAM affect everything from artificial intelligence platforms to IoT sensor nodes. There is a huge power and performance overhead when the various IP blocks in an SOC need to go to DRAM. Memory caches have become essential to SOC design to reduce these adverse effects. However, … Read More
Enterprise SSD SOC’s Call for a Different Interconnect Approach
The move to SSD storage for enterprise use brings with it the need for difficult to design enterprise capable SSD controller SOC’s. The benefits of SSD in hyperscale data centers are clear. SSD’s offer higher reliability due to the elimination of moving parts. They have a smaller foot print, use less power and offer much better performance.… Read More
Smart TV Chipset: 4 Key Takeaways from Interconnect IP
The ultra high-definition (UHD) or 4K TV hardware is leading to insanely powerful chipsets in the age of Netflix, and that is taking the system-on-chip (SoC) design to a whole new level of complexity. Take the case of Samsung’s new chipset for SUHD TVs that boasts more than 100 IP interfaces.
Here, apart from the usual suspects… Read More
How Wireless Modem IP is Aiding Roadmap to 5G Chipsets
The semiconductor industry is steadily charting its course toward 5G chipsets with the availability of extremely complex system-on-chip (SoC) designs that support the surge of data traffic over next-generation wireless networks. Take Blu Wireless Technology, for instance, the IP supplier from Britain that is using the Arteris… Read More
Optimizing Quality-of-Service in a Network-on-Chip Architecture
The Linley Group is well-known for their esteemed Microprocessor Report publication, now in its 28th year. Accompanying their repertoire of industry reports, TLG also sponsors regular conferences, highlighting the latest developments in processor architecture and implementation.
One of the highlights of the conference… Read More
Automating Timing Closure Using Interconnect IP, Physical Information
Timing closure is a “tortoise” for some system-on-chip (SoC) designers just the way many digital guys call RF design a “black art”. Chip designers often tell horror stories of doing up to 20 back-end physical synthesis place & route (SP&R) iterations with each iteration taking a week or more. “Timing closure”, a largely… Read More
Arteris Flexes Networking Muscle in TI’s Multi-standard IoT Chip
Arteris Inc., a network-on-chip (NoC) interconnect IP solution provider, has joined hands with Texas Instruments Inc. to create an ultra-low-power chip that helps Internet of Things (IoT) devices go battery-less with energy harvesting and support coin cell-powered IoT operation for multiple years.
Another low-power MCU… Read More
Sonics vs Arteris Lawsuit Update!
As strange as it may seem one of my hobbies is reading case law. It’s not only interesting to see what the human race is really up to, it is also good to know your rights in regards to things like defamation, especially when you are a New Media mogul like myself. Some of the funnier defamation cases are called “Twibel” as in libel on Twitter.… Read More