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WP_Term Object
(
    [term_id] => 89
    [name] => FinFET
    [slug] => finfet
    [term_group] => 0
    [term_taxonomy_id] => 89
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 227
    [filter] => raw
    [cat_ID] => 89
    [category_count] => 227
    [category_description] => 
    [cat_name] => FinFET
    [category_nicename] => finfet
    [category_parent] => 0
    [is_post] => 
)
FinFET
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Place & Route with FinFETs and Double Patterning

Place & Route with FinFETs and Double Patterning
by Paul McLellan on 09-29-2014 at 8:00 am
Categories: EDA, FinFET

Place & route in the 16/14nm era requires a new approach since it is significantly more complex. Of course, every process generation is more complex than the one before and the designs are bigger. But modern processes have new problems. The two biggest changes are FinFETs and double patterning.

FinFETs, as I assume you know,… Read More

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Samsung 14nm FinFET Design with Cadence Tools

Samsung 14nm FinFET Design with Cadence Tools
by Daniel Payne on 09-22-2014 at 5:30 pm
Categories: Cadence, EDA, FinFET, Foundries, Samsung Foundry

The first consumer products with 20nm processing are arriving in 2014 like the 2 billion transistor A8 chip in the iPhone 6, however at the 14nm node there are new designs underway to continue the trend of Moore’s Law. To get a better feel for the challenges of designing with 14nm FinFET technology I watched a 23 minute video … Read More

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FinFET Design for Power, Noise and Reliability

FinFET Design for Power, Noise and Reliability
by Daniel Payne on 08-29-2014 at 4:00 pm
Categories: Ansys, Inc., EDA, FinFET

IC designers have been running analysis tools for power, noise and reliability for many years now, so what is new when you start using FinFET transistors instead of planar transistors? Calvin Chow from ANSYS (Apache Design) presented on this topic earlier in the summer through a 33 minutewebinar that has been archived. There is… Read More

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FinFETs for your Next SoC

FinFETs for your Next SoC
by Daniel Payne on 08-24-2014 at 7:00 am
Categories: EDA, FinFET, Synopsys

Planar CMOS processes have been offered for decades now, and all the way down through the 28nm node it has been riding the benefits of Moore’s Law. A few years back we started hearing from Intel about TriGate (aka FinFET) starting at the 22nm node as a way to use a more 3D processing approach for transistors instead of planar CMOS.… Read More

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What Comes After FinFET?

What Comes After FinFET?
by Paul McLellan on 08-10-2014 at 11:01 pm
Categories: ESD Alliance, FinFET, Semiconductor Services

So what comes after FinFETs? At 14/16nm (or 22nm if you are Intel) we had FinFET transistors, where the channel was no longer planar but stuck out of the wafer vertically, and the gate wrapped around it on 3 sides. The key thing that made FinFET transistors attractive was that the channel was thin so that the gate controlled it well. … Read More

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Altera vs Xilinx FinFET Update

Altera vs Xilinx FinFET Update
by Daniel Nenni on 07-27-2014 at 10:10 am
Categories: FinFET, FPGA, Xilinx

One of the things I do in my spare time is listen to quarterly conference calls and try to sort fact from fiction. I compare past calls to the current one and attempt to predict what’s coming next. Confucius said, “Study the past if you would define the future” and I’m a big believer in that.

Paul McLellan wrote about the Xilinx call earlier… Read More

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FinFET Based Designs Made Easy & Reliable

FinFET Based Designs Made Easy & Reliable
by Pawan Fangaria on 06-15-2014 at 11:00 am
Categories: Ansys, Inc., EDA, FinFET

Although semiconductor manufacturing has taken off with FinFET based process technology which provides lucrative payoffs on performance improvement, power reduction and area saving in devices for high density and high performance SoC demand of modern era, apprehensions remain about its reliability due to reduced noise … Read More

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Xilinx’s 16nm vs. Altera 14nm

Xilinx’s 16nm vs. Altera 14nm
by Luke Miller on 06-04-2014 at 8:00 pm
Categories: FinFET

You will not believe this, but the family was picking me up Friday evening from the airport and on the way home… Get this, for real, the wife asks me to cut her hair tomorrow. Now the three of you that read my stuff, know what happened before. I resisted, and firmly said ‘No’…The wife seeing my macho stance began appealing to my engineer’s… Read More

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IC Power Noise Reliability for FinFET Designs

IC Power Noise Reliability for FinFET Designs
by Daniel Payne on 05-06-2014 at 9:07 am
Categories: Ansys, Inc., EDA, FinFET

Reliability for ICs is a big deal because the last thing that you want to do is ship a new part only to find out later in the field that there are failures not being caught by testing. I’ve already had two consumer products fail this year because of probable reliability issues: My MacBook Pro with 16GB of RAM started rebooting caused… Read More

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The Infamous Intel FPGA Slide!

The Infamous Intel FPGA Slide!
by Daniel Nenni on 03-11-2014 at 10:30 am
Categories: FinFET, Foundries, FPGA, Intel Foundry, TSMC, Xilinx

As I have mentioned before, I’m part of the Coleman Research Group so you can rent me by the hour to better understand the semiconductor industry. Most of the conversations are by phone but sometimes I do travel to the East Coast, Taiwan, Hong Kong, and China for face-to-face meetings. Generally the calls are the result of an event … Read More