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A moment of IoT silence before we disrupt

A moment of IoT silence before we disrupt
by Don Dingee on 11-08-2015 at 12:00 pm

As I sat down in the SEMI Arizona Chapter breakfast meeting a few weeks ago, a moment of semiconductor history flew right before my eyes before the IoT sessions started.

We were seated in the cafeteria of Freescale Building 94 on Elliot Road in Tempe, a place I’d been many times before, except this time may have been the last. NXP is consolidating… Read More


Moore’s Law and Silicon Forest

Moore’s Law and Silicon Forest
by Daniel Payne on 11-04-2015 at 4:00 pm

When I first moved to Oregon in 1978 the largest industry was forestry, but then the endangered Spotted Owl was found and that put an end to many forestry companies and decimated the economy of many rural cities. Strangely enough it turns out that the Spotted Owl was found in great numbers across multiple states, so it never should’ve… Read More


SEMI Releases Industry’s First “Global 200mm Fab Outlook to 2018” and Announces Webinar

SEMI Releases Industry’s First “Global 200mm Fab Outlook to 2018” and Announces Webinar
by Deborah GeigerSEMI on 10-19-2015 at 1:30 pm

SEMI, the global industry association advancing the interests of the worldwide electronics supply chain, today (October 19) published a new report, “Global 200mm Fab Outlook to 2018.” According to the report, worldwide 200mm semiconductor wafer fab capacity is forecast at 5.2 million wafer starts per month (wspm) in 2015 andRead More


Wafer-Level Chip-Scale Packaging Technology Challenges and Solutions

Wafer-Level Chip-Scale Packaging Technology Challenges and Solutions
by Tom Dillinger on 10-15-2015 at 7:00 am

At the recent TSMC OIP symposium, Bill Acito from Cadence and Chin-her Chien from TSMC provided an insightful presentation on their recent collaboration, to support TSMC’s Integrated FanOut (InFO) packaging solution. The chip and package implementation environments remain quite separate. The issues uncovered in bridging… Read More


IMEC and Cadence Disclose 5nm Test Chip

IMEC and Cadence Disclose 5nm Test Chip
by Scotten Jones on 10-09-2015 at 7:00 am

Recently imec and Cadence disclosed that they had fabricated 5nm test chips. This afternoon Dan Nenni and I had a conference call with Praveen Raghavan, principal engineer at imec, and Vassilios Gerousis, distinguished engineer at Cadence to get more details on what the test chip is and what was learned.

First off Vassilios really… Read More


Cadence Outlines Automotive Solutions at TSMC OIP Event

Cadence Outlines Automotive Solutions at TSMC OIP Event
by Tom Simon on 10-08-2015 at 12:00 pm

I used to joke that my first car could survive a nuclear war. It was a 1971 Volvo sedan (142) that was EMP proof because it had absolutely no semiconductors in the ignition system, just points, condensers and a coil. If you go back to the Model T in 1915 you will see that the “on-board electronics” were not that different. However, today’s… Read More


EDA By the Numbers, Phil Kaufman, Emerging Companies and More

EDA By the Numbers, Phil Kaufman, Emerging Companies and More
by Paul McLellan on 10-01-2015 at 7:00 am

The quarterly numbers are out from the EDAC Market Statistics Service (MSS) for Q2. The headline number is that revenue for the industry increased by 8.5% for Q2 to $1906.5M versus $1759.9M in Q2 last year. The four quarter moving average, that smooths out a lot of seasonality by comparing the most recent four quarters to the prior… Read More


Xilinx Skips 10nm

Xilinx Skips 10nm
by Paul McLellan on 09-28-2015 at 7:00 am

At TSMC’s OIP Symposium recently, Xilinx announced that they would not be building products at the 10nm node. I say “announced” since I was hearing it for the first time, but maybe I just missed it before. Xilinx would go straight from the 16FF+ arrays that they have announced but not started shipping, and to the… Read More


SEMICON West Preview

SEMICON West Preview
by Scotten Jones on 07-07-2015 at 7:00 am

Founded in 1971 (2015: 45th year), SEMICON West 2015 is coming to the Moscone Center in San Francisco on from Tuesday, July 14[SUP]th[/SUP] to Thursday, July 16[SUP]th[/SUP]. SEMICON is the premier show for equipment and materials companies supporting the semiconductor, MEMS and solar industries.

The main ways to get value … Read More


Unlock the Key to Ultra-Low Power Design

Unlock the Key to Ultra-Low Power Design
by Tom Simon on 06-20-2015 at 7:00 am

We have been hearing about low power for a long time. Fortunately, low power chip operation has come about through a large number of innovations. Key among these is clock gating, frequency and voltage scaling, managing leakage with lower threshold voltage, HKMG, and many other techniques. But we are entering the age of ultra low… Read More