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Challenges in 3D-IC and 2½D Design

Challenges in 3D-IC and 2½D Design
by Paul McLellan on 12-09-2011 at 5:18 pm

3D IC design and what has come to be known as 2½D IC design, with active die on a silicon interposer, require new approaches to verification since the through silicon vias (TSVs) and the fact that several different semiconductor processes may be involved create a new set of design challenges

The power delivery network is a challenge… Read More


Improving Analog/Mixed Signal Circuit Reliability at Advanced Nodes

Improving Analog/Mixed Signal Circuit Reliability at Advanced Nodes
by glforte on 12-07-2011 at 3:52 pm

Preventing electrical circuit failure is a growing concern for IC designers today. Certain types of failures such as electrostatic discharge (ESD) events, have well established best practices and design rules that circuit designers should be following. Other issues have emerged more recently, such as how to check circuits… Read More


How Fast (and accurate) is Your SPICE Circuit Simulator?

How Fast (and accurate) is Your SPICE Circuit Simulator?
by Daniel Payne on 12-06-2011 at 6:17 pm

In my dad’s generation they tweaked cars to become hotrods while in EDA today we have companies that tweak SPICE circuit simulators to become crowned speed champions. The perennial question though is, “How fast and accurate is my SPICE circuit simulator?”… Read More


Methodics can Now use www.methodics.com after Domain Name Battle in EDA

Methodics can Now use www.methodics.com after Domain Name Battle in EDA
by Daniel Payne on 12-06-2011 at 5:36 pm

Imagine trying to run your EDA business only to have a competitor squat on your domain name and then make disparaging remarks about you. This sounds like a match made for reality TV however it is quite real, and now this chapter in EDA has a happy ending because Methodics can use www.methodics.com as their domain name.


The Bad Guy
We’ve… Read More


EDA mergers: Accelicon acquired by Agilent

EDA mergers: Accelicon acquired by Agilent
by Daniel Payne on 12-06-2011 at 4:51 pm

Agilent acquired EEsof back in 1999, now the EEsof group acquired Accelicon on December 1, 2011. The terms of the deal are not disclosed.

SPICE circuit simulators are only as accurate as their models and algorithms. On the model side we have Accelicon that provides EDA tools to create SPICE models based on silicon measurements:… Read More


HSPICE – I Didn’t Know That About IC Circuit Simulation

HSPICE – I Didn’t Know That About IC Circuit Simulation
by Daniel Payne on 12-05-2011 at 11:14 am

HSPICE is over 30 years old, which is a testimony of how solid the circuit simulator has been and how widely used it is. To stay competitive the HSPICE developers have to innovate or the product will slowly loose ground to the many other simulator choices. I listened to the webinar last week to find out what was new with HSPICE.

SzekitRead More


Interoperability Forum

Interoperability Forum
by Paul McLellan on 12-03-2011 at 3:19 pm


Earlier this week I went to the Synopsys Interoperability Forum. The big news of the day turned out to be Synopsys wanting to be more than interoperable with Magma, but that only got announced after we’d all gone away.

Philippe Margashack of ST opened, reviewing his slides from a presentation at the same forum from 10 years … Read More


A Review of an Analog Layout Tool called HiPer DevGen

A Review of an Analog Layout Tool called HiPer DevGen
by Daniel Payne on 11-28-2011 at 1:11 pm

My last IC design at Intel was a Graphics Chip and I developed a layout generator for Programmable Logic Arrays (PLA) that automated the task, so I’ve always been interested in how to make IC layout more push-button and less polygon pushing. Today I watched a video about HiPer DevGen from Tanner EDA and wanted to share what I … Read More


December 1st – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)

December 1st – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)
by Daniel Payne on 11-24-2011 at 9:57 am

I’ve blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is BetterRead More


How to use NoC to avoid routing congestion

How to use NoC to avoid routing congestion
by Eric Esteve on 11-23-2011 at 5:21 am

Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. Sgroi et al. call “the layered-stack approach to the design of the on-chip intercore communications the Network-on-Chip (NOC) methodology.” In a NoC system, modules such as processorRead More