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View from the top: Ajoy Bose

View from the top: Ajoy Bose
by Paul McLellan on 12-12-2011 at 4:13 pm

 I sat down yesterday with Dr. Ajoy Bose, CEO of Atrenta, to get his view of the future of EDA – looking through a high-power “spyglass” of sorts. I first met Ajoy when he was at Software & Technologies. I was then the VP of Engineering for Compass Design Automation and we were considering off-shoring some development. We eventually dipped a toe in the water with small groups in both India (at Hyderabad) and Moscow. The feel of India from inside a high-tech company building is very different from the feel outside on the street, but that’s a story for another day.

Ajoy believes that what Cadence calls SOC Realization in their EDA360 white paper is a transformation of how design is done that is as great as the move from schematics to RTL, although just as then, it is a transformation that takes years to complete.

We talked about the fact that chips are no longer really designed at the RTL level – they are assemblies of IP blocks. But IP quality and other design meta-data is lacking in standard representations in the design flow, which is getting to be a big problem. Hmm, sounds like the interoperability forum I was at earlier in the week.

Ajoy believes the Holy Grail is early exploration, making sure a design meets its targets for power, performance and area well before you commit to detailed implementation. This process requires more collaboration within the ecosystem, along with standards for IP creation, IP assembly and SoC assembly. One opportunity is solving problems early and only once in the design cycle, which requires additional information in the form of constraints and waivers.

We also talked about the fact we need a much better way to abstract a block. For physical design, we can take a block and “black-box” it, just needing to know where the terminals are. But for IP blocks it’s not that easy. You can’t do IP-based design the way you used to be able to take your TI 7400 series databook and do printed circuit board design. IP doesn’t work like that for timing, or for testability. Much more detailed information needs to be processed to get a useful answer. The same is true for power consumption.

Of course another big change is that software forms more and more of the design. This is seen most clearly at Apple where software is the king. Apple builds chips especially optimized to run exactly the required software load.

 Ajoy reckons that about 10% of design groups are taking all this into account and doing design that starts with the software and then designing the hardware using the software to focus that development. The other 90% design the chip and then let the software guys have at it, which is much slower and less predictable.

From an EDA business point of view it is clear that the system companies are taking more control. These types of companies seem to be prepared to pay for tools that deliver value. Since they are not already making enormous purchases of less differentiated stuff they seem less inclined to insist that everything is simply rolled into an all-you-can-eat deal for next to nothing.

There is a chance that design handoff will move to this block level, the level that specifies the virtual platform for the software people and the IP to be assembled for the SoC team. It is still early, but Ajoy and Atrenta believe the change is coming.

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