SILVACO 073125 Webinar 800x100
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Aldec-Altera DO-254

Aldec-Altera DO-254
by Daniel Nenni on 09-25-2012 at 9:58 pm

As described in DO-254, any inability to verify specific requirements by test on the device itself must be justified, and alternative means must be provided. Certification authorities favor verification by test for formal verification credits because of the simple fact that hardware flies not simulation models. RequirementsRead More


Jasper User Group

Jasper User Group
by Paul McLellan on 09-25-2012 at 1:19 pm

The Jasper User Group meeting has been announced. It will take place on November 12th and 13th. As last year, it will be at the Cypress Hotel at 10050 De Anza Boulevard in Cupertino. The user group meeting is free for qualified Jasper customers.

Topics to be covered are, of course, all things verification:

  • SoC subsystems verification
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Chip Aware System Design

Chip Aware System Design
by Paul McLellan on 09-24-2012 at 5:45 pm

On Wednesday this week Ansys/Ansoft/Apache are presenting a new webinar Chip Aware System Design. It is presented by Dr Steven Gary Pytel Jr of the Ansoft part of Ansys, and Matt Elmore of the Apache subsidiary. The topics that will be covered include:

  • Power Delivery Network (PDN) design requirements
  • ABCD Matrix theory
  • SYZ Matrix
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SAME 2012 Conference on October 2-3 in Sophia is coming soon!

SAME 2012 Conference on October 2-3 in Sophia is coming soon!
by Eric Esteve on 09-24-2012 at 11:01 am

This is the 15[SUP]th[/SUP] anniversary for the SAME Conference, dedicated to innovation on Microelectronics. Sophia-Antipolis is not only close to Mediterranean sea, but also at the heart of Telecom valley in south of France, with Texas Instruments design center dedicated to Application Processor design (OMAP), Cadence… Read More


Cadence Mixed Signal Technology Summit

Cadence Mixed Signal Technology Summit
by Paul McLellan on 09-21-2012 at 6:46 pm

Yesterday I attended some of the Cadence mixed-signal technology summit. The day ended with a panel session on Are We Closing the Gap Yet in Mixed-signal Design? Richard Goering moderated. The panelists were all mixed signal experts:

  • Nayaz Khan of Maxim
  • Nishant Shah of Broadcom
  • Shiv Sikand of IC Manage
  • Bill Meier of Texas Instruments
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Atrenta Wins Gold

Atrenta Wins Gold
by Paul McLellan on 09-21-2012 at 6:16 pm

What is the most read article on design on EE Times website? Brian Bailey has an article up running through the top 10. It turns out that the #1 article is Understanding Clock Domain Issues by Saurabh Verma and Ashima S. Dabare of Atrenta. It actually had more than double the views of the second place paper. Checking clock domain crossing… Read More


Displaced but Looking to Add EDA Tools Skills?

Displaced but Looking to Add EDA Tools Skills?
by Daniel Payne on 09-21-2012 at 1:12 pm

In this tough economy you may find yourself displaced and looking for the next opportunity. If you’d like to add some new EDA tool skills, then check out what EMA Design Automation is offering with free Cadence OrCAD training.… Read More


Virtual Prototype your SoC including Arteris FlexNoC and optimize architecture using CPAK from Carbon

Virtual Prototype your SoC including Arteris FlexNoC and optimize architecture using CPAK from Carbon
by Eric Esteve on 09-21-2012 at 7:37 am

I have talked about Virtual Prototyping a SoC including FlexNoC Network on Chip IP from Arteris by using Carbon Design Systems set of tools in a previous post. A blog, posted on Carbon’ web, is clearly explaining the process to follow to optimize a fabric (FlexNoC) successively using the different tools from Carbon. Bill Neifert,… Read More


Automating Complex Circuit Checking Tasks

Automating Complex Circuit Checking Tasks
by SStalnaker on 09-20-2012 at 7:24 pm

By Hend Wagieh, Mentor Graphics

At advanced IC technology nodes, circuit designers are now encountering problems such as reduced voltage supply headroom, increased wiring parasitic resistance (Rp) and capacitance (Cp), more restrictive electromigration (EM) rules, latch-up, and electrostatic discharge (ESD) damage,… Read More


Schematic Capture, Analog Fast SPICE, and Analysis Update

Schematic Capture, Analog Fast SPICE, and Analysis Update
by Daniel Payne on 09-20-2012 at 1:10 pm

At the DAC show in June I met with folks at Berkeley DA and heard about their Analog Fast SPICE simulator being used inside of the Tanner EDA tools. With the newest release from Tanner called HiPer Silicon version 15.23 you get a tight integration between:… Read More