Wanna become the double patterning guru at your company? David Abercrombie, DFM Program Manager for Calibre, has written a series of articles detailing the multifaceted impacts of double patterning on advanced node design and verification. For designers struggling to understand the complexity and nuances of double patterning,… Read More
Electronic Design Automation
SystemC vs C++ for High Level Synthesis
One of the decisions that needs to be made when using high-level synthesis (HLS) in general and Catapult in particular is what language to use as input. The choice is C++ or SystemC. Of course at some level SystemC is C++ with added libraries and templates, but in fact the semantics of the two languages end up being very different.
The… Read More
An FPGA Design Flow with Aldec Tools
I’ve used FPGA vendor-supplied tools from both Xilinxand Lattice Semibefore, so I wanted to see what EDA tools Aldec has to offer for FPGA design. I read the Aldecwhite paper, Corporate Standardization of FPGA Design Flow, and summarize what I found.… Read More
Mixed-Signal Methodology Guide: Design Management
I reviewed the book Mixed-Signal Methodology Guidein August of this year published by Cadence, and decided to follow up with one of the authors, Michael Henrie from ClioSoft, to learn more about the importance of Design Management for AMS. Michael is a Software Engineering Manager at ClioSoft and has worked at Zarlink Semi, Legerity,… Read More
Variation-Aware Design: A Hands-on Field Guide
IC designers using advanced nodes are acutely aware of how variation effects in the silicon itself are causing increased analysis and design efforts in order to yield chips at acceptable levels. Four authors from Solidoare so passionate about this topic that they combined their years of experience into a book that I had a chance… Read More
Sequential Power Optimization
Calypto has an interesting webinar coming up about Minimizing RTL Power Through Sequential Analysis. It is next Tuesday December 4th at 11am.
Insert standard paragraph about how power is the new timing, everyone worries about power, battery life in smartphones, half-empty datacenters.
You probably already know about clock… Read More
GLOBALFOUNDRIES and Mentor Develop Methods to Identify Critical Features in IC Designs
Since the beginning of the semiconductor industry, improving the rate of yield learning has been a critical factor in the success silicon manufacturing. Each fab has dedicated yield teams that look at the yield of wafers manufactured the previous day and attempt to find the root cause of any unexpected “excursions.” In earlier… Read More
AMS IC Design at Rohde & Schwarz
I met Frank Wiedmann on LinkedIn because we are both members of the Analog Mixed Signal group, and he has an interesting background in AMS IC design.
Since he lives in Munich we conducted our interview by email.… Read More
Give me a pair of wires, I’ll give you Ethernet in cars
A very astute gentleman said to me a few years ago that he’d seen a lot of networking technology come and go – Token Ring, FDDI, Fibre Channel, InfiniBand – but the only one that held up over time was Ethernet.… Read More
Second FPGA to the right, and straight on ‘til it works
In a fantasy world where there were no coding errors or integration issues, FPGA designs would fly straight through synthesis easily and quickly. Maybe that world does exist somewhere. For the rest of us, who have experienced the agony of running a large FPGA design – again – only to find another error and have to start over, there … Read More
Facing the Quantum Nature of EUV Lithography