CAST Compression IP Webinar 800x100 (2)
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EDA

Electronic Design Automation

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Happy Holidays

Happy Holidays
by Paul McLellan on 12-10-2012 at 3:00 pm
Categories: EDA

At times of this year, companies usually get their salespeople to submit the names and addresses of all their customers. They then get an expensive card printed and mail it out. What the recipient does is anyone’s guess, from throwing it straight in the bin to using it to decorate the office.

Atrenta decided to do something … Read More

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Zynq out of the box, in FPGA-based prototyping

Zynq out of the box, in FPGA-based prototyping
by Don Dingee on 12-10-2012 at 11:24 am
Categories: Aldec, EDA, FPGA

Roaming around the hall at ARM TechCon 2012 left me with eight things of note, but one of the larger ideas showing up everywhere is the Xilinx Zynq. Designers are enthralled with the idea of a dual-core ARM Cortex-A9 closely coupled with programmable logic.… Read More

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Double Patterning Verification

Double Patterning Verification
by Paul McLellan on 12-10-2012 at 3:03 am
Categories: EDA, Synopsys

You can’t have failed to notice that 20nm is coming. There are a huge number of things that are different about 20nm from 28nm, but far and away the biggest is the need for double patterning. You probably know what this is by now, but just in case, here is a quick summary.

Lithography is done using 193nm light. Today we use immersion… Read More

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Apache Power Artist Capabilities II

Apache Power Artist Capabilities II
by Paul McLellan on 12-09-2012 at 4:00 pm
Categories: Ansys, Inc., EDA

This is the second part of my discussion with Paul Traynar, Apache’s PowerArtist guru. The first part discussed sequential reduction capabilities. Part I was here.

There are two big challenges with doing power analysis at the RTL level. Firstly, how do you get an accurate enough model of what the design will dissipate given… Read More

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Subsystem IP, myth or reality?

Subsystem IP, myth or reality?
by Eric Esteve on 12-07-2012 at 5:00 am
Categories: Cadence, IP

I have participated to a panel during IP-SoC, I must say that “Subsystem IP, myth or Reality” was a great moment. The panel was a mix of mid-size IP vendor (CAST, Sonics), one large EDA (Martin Lund from Cadence), Semiwiki blogger and one large IDM (Peter Hirt from STM) who has very well represented the customer side. And, to make the… Read More

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Yield Analysis and Diagnosis Webinar

Yield Analysis and Diagnosis Webinar
by Beth Martin on 12-06-2012 at 10:02 pm
Categories: EDA, Siemens EDA

Sign up for a free webinar on December 11 on Accelerating Yield and Failure Analysis with Diagnosis.

The one hour presentation will be delivered via webcast by Geir Eide, Mentor’s foremost expert in yield learning. He will cover scan diagnosis, a software-based technique, that effectively identifies defects in digital logic… Read More

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Apache Power Artist Capabilities I

Apache Power Artist Capabilities I
by Paul McLellan on 12-06-2012 at 2:05 pm
Categories: Ansys, Inc., EDA

I sat down last week with Paul Traynar who was over from UK. He is Apache’s PowerArtist guru. The first thing we talked about was PowerArtist’s sequential power reduction capabilities.

Forward propagation of enables means that when a register is clock gated and feeds a downstream register then that register can be… Read More

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A Brief History of the Fabless Semiconductor Ecosystem

A Brief History of the Fabless Semiconductor Ecosystem
by Daniel Nenni on 12-05-2012 at 7:00 pm
Categories: EDA, Foundries, IP

Clearly the fabless semiconductor ecosystem is driving the semiconductor industry and is responsible for both the majority of the innovation and the sharp decline in consumer electronics costs we have experienced. By definition, a fabless semiconductor company does not have to spend the time and money on manufacturing related… Read More

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Microprocessor Test and Verification 2012

Microprocessor Test and Verification 2012
by Paul McLellan on 12-05-2012 at 5:43 pm
Categories: EDA

Next week December 10-12th is the Microprocessor Test and Verification (MTV 2012) which is in Austin Texas (as DAC will be next year, of course). After lunch on Monday there is a panel session on the effectiveness of virtual prototyping entitled When simulation suffices, who needs FPGA or emulation? Bill Neifert, the CTO of Carbon… Read More

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Formal Analysis of Security Data Paths

Formal Analysis of Security Data Paths
by Paul McLellan on 12-05-2012 at 5:07 pm
Categories: EDA

One challenge with security in systems is to ensure that there are not backdoors, either accidentally or maliciously inserted. Intel, ARM and others have various forms of trusted execution technology. Under the hood these are implemented by dividing the design into two parts, normal and secure, and implementing them with physical… Read More