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EDA

Electronic Design Automation

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Shorter, better and easier PCIe and NVM Express Verification flow with advanced technologies

Shorter, better and easier PCIe and NVM Express Verification flow with advanced technologies
by Eric Esteve on 07-19-2012 at 8:05 pm
Categories: Cadence, IP

We have talked about Cadence subsystem IP strategy, illustrated by NVM Express subsystem IP, in a previous blog. What we said was that “A subsystem IP based approach will also speed up the software development and validation phase: if the IP provider is able to propose the right tools, like the associated Verification IP (VIP), … Read More

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It Takes a Village: Mentor and ARM Team Up on Test

It Takes a Village: Mentor and ARM Team Up on Test
by Beth Martin on 07-18-2012 at 5:01 pm
Categories: Arm, EDA, IP, Siemens EDA

Benjamin Franklin, “I didn’t fail the test, I just found 100 ways to do it wrong.” I was reminded of this line during a joint Mentor-ARM seminar yesterday about testing ARM cores and memories. The complexity of testing modern SoC designs at advanced nodes, with multiple integrated ARM cores and other IP, opens up plenty of room for… Read More

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How Do You Extract 3D IC Structures?

How Do You Extract 3D IC Structures?
by Daniel Payne on 07-18-2012 at 2:01 pm
Categories: EDA, Siemens EDA

The press has been buzzing about 3D everything for the past few years, so when it comes to IC design it’s a fair question to ask how would you actually extract 3D IC structures for use by analysis tools like a circuit simulator. I read a white paper by Christen Decoin and Vassilis Kourkoulos of Mentor Graphics this week and became… Read More

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EDAC Announces EDA up 6.3% in Q1 versus 2011

EDAC Announces EDA up 6.3% in Q1 versus 2011
by Paul McLellan on 07-17-2012 at 11:24 pm
Categories: EDA

EDAC announced that EDA industry revenue increased 6.3% for Q1 2012 to $1536.9M compared to a year ago. Sequentially it declined, as it normally does from Q4 to Q1, by 9.6%. Every category except services increased revenue and every region increased revenue except for Japan. The full report is available by subscription, of course.… Read More

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Design-to-Silicon Platform Workshops!

Design-to-Silicon Platform Workshops!
by Daniel Nenni on 07-17-2012 at 7:30 pm
Categories: EDA, Siemens EDA

Have you seen the latest design rule manuals? At 28nm and 20nm design sign-off is no longer just DRC and LVS. These basic components of physical verification are being augmented by an expansive set of yield analysis and critical feature identification capabilities, as well as layout enhancements, printability, and performance… Read More

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3D Thermal Analysis

3D Thermal Analysis
by Paul McLellan on 07-17-2012 at 11:32 am
Categories: Ansys, Inc., EDA

Matt Elmore of ANSYS/Apache has an interesting blog posting about thermal analysis in 3D integrated circuits. With both technical and economic challenges at process nodes as we push below 28nm, increasingly product groups are looking towards through-silicon-via (TSV) based approaches as a way of keeping Moore’s law… Read More

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An Approach to 20nm IC Design

An Approach to 20nm IC Design
by Daniel Payne on 07-17-2012 at 10:10 am
Categories: Cadence, EDA

Last month at DAC I learned how IBM, Cadence, ARM, GLOBALFOUNDRIES and Samsung approach the challenges of SoC design, EDA design and fabrication at the 20nm node. Today I followed up by reading a white paper on 20nm IC design challenges authored by Cadence, a welcome relief to the previous marketing mantra of EDA 360.

Here’s… Read More

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How has 20nm Changed the Semiconductor Ecosystem?

How has 20nm Changed the Semiconductor Ecosystem?
by Daniel Nenni on 07-15-2012 at 7:30 pm
Categories: Cadence, EDA, Foundries, TSMC


What does mango beer have to do with semiconductor design and manufacturing? At a table of beer drinkers from around the world I would have never thought fruity beer would pass a taste test, not even close. As it turns out, the mango beer is very good! Same goes for 20nm planar devices. “Will not work”, “Will not yield”, “Will not scale”,… Read More

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Scoreboards and Results Predictors in UVM

Scoreboards and Results Predictors in UVM
by Daniel Nenni on 07-15-2012 at 10:56 am
Categories: EDA, Siemens EDA

If verification is the art of determining that your design works correctly under all specified conditions, then it is imperative that we are able to create an environment that can tell you if this is truly the case.

Scoreboards are verification components that determine that the DUT is working correctly, including ensuring that… Read More

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Using Accurate Models to Debug Cellphones

Using Accurate Models to Debug Cellphones
by Paul McLellan on 07-13-2012 at 10:54 am
Categories: EDA

There is an interesting Gizmodo review of an HTC Android-based smartphone. The basically positive review (as good as the iPhone, best Android phone at the time) ends up with an update:UPDATE: After more extensive testing there’s something a little weird going on. You’ll probably only see this while gaming, but there’s… Read More