hip webinar automating integration workflow 800x100 (1)
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EDA

Electronic Design Automation

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MemCon Returns

MemCon Returns
by Paul McLellan on 07-25-2012 at 9:44 am
Categories: Cadence, EDA

Back before Denali was acquired by Cadence they used to run an annual conference called MemCon. Since Denali was the Switzerland of EDA, friend of everyone and enemy of none, there would be presentations from other memory IP companies and from major EDA companies. For example, in 2010, Bruggeman, then CMO of Cadence, gave the opening… Read More

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How Many Licenses Do You Buy?

How Many Licenses Do You Buy?
by Paul McLellan on 07-23-2012 at 6:16 pm
Categories: EDA

An informal survey of RTDA customers reveals that larger companies tend to buy licenses based on peak usage while smaller companies do not have that luxury and have to settle for fewer licenses than they would ideally have and optimize the mix of licenses that they can afford given their budget. Larger companies get better prices… Read More

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Libraries Make a Power Difference in SoC Design

Libraries Make a Power Difference in SoC Design
by Daniel Payne on 07-23-2012 at 4:37 pm
Categories: EDA, Synopsys

ken brock

At Intel we used to hand-craft every single transistor size to eek out the ultimate in IC performance for DRAM and graphic chips. Today, there are many libraries that you can choose from for an SoC design in order to reach your power, speed and area trade-offs. I’m going to attend a Synopsys webinar on August 2nd to learn more … Read More

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Shorter, better and easier PCIe and NVM Express Verification flow with advanced technologies

Shorter, better and easier PCIe and NVM Express Verification flow with advanced technologies
by Eric Esteve on 07-19-2012 at 8:05 pm
Categories: Cadence, IP

We have talked about Cadence subsystem IP strategy, illustrated by NVM Express subsystem IP, in a previous blog. What we said was that “A subsystem IP based approach will also speed up the software development and validation phase: if the IP provider is able to propose the right tools, like the associated Verification IP (VIP), … Read More

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It Takes a Village: Mentor and ARM Team Up on Test

It Takes a Village: Mentor and ARM Team Up on Test
by Beth Martin on 07-18-2012 at 5:01 pm
Categories: Arm, EDA, IP, Siemens EDA

Benjamin Franklin, “I didn’t fail the test, I just found 100 ways to do it wrong.” I was reminded of this line during a joint Mentor-ARM seminar yesterday about testing ARM cores and memories. The complexity of testing modern SoC designs at advanced nodes, with multiple integrated ARM cores and other IP, opens up plenty of room for… Read More

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How Do You Extract 3D IC Structures?

How Do You Extract 3D IC Structures?
by Daniel Payne on 07-18-2012 at 2:01 pm
Categories: EDA, Siemens EDA

The press has been buzzing about 3D everything for the past few years, so when it comes to IC design it’s a fair question to ask how would you actually extract 3D IC structures for use by analysis tools like a circuit simulator. I read a white paper by Christen Decoin and Vassilis Kourkoulos of Mentor Graphics this week and became… Read More

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EDAC Announces EDA up 6.3% in Q1 versus 2011

EDAC Announces EDA up 6.3% in Q1 versus 2011
by Paul McLellan on 07-17-2012 at 11:24 pm
Categories: EDA

EDAC announced that EDA industry revenue increased 6.3% for Q1 2012 to $1536.9M compared to a year ago. Sequentially it declined, as it normally does from Q4 to Q1, by 9.6%. Every category except services increased revenue and every region increased revenue except for Japan. The full report is available by subscription, of course.… Read More

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Design-to-Silicon Platform Workshops!

Design-to-Silicon Platform Workshops!
by Daniel Nenni on 07-17-2012 at 7:30 pm
Categories: EDA, Siemens EDA

Have you seen the latest design rule manuals? At 28nm and 20nm design sign-off is no longer just DRC and LVS. These basic components of physical verification are being augmented by an expansive set of yield analysis and critical feature identification capabilities, as well as layout enhancements, printability, and performance… Read More

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3D Thermal Analysis

3D Thermal Analysis
by Paul McLellan on 07-17-2012 at 11:32 am
Categories: Ansys, Inc., EDA

Matt Elmore of ANSYS/Apache has an interesting blog posting about thermal analysis in 3D integrated circuits. With both technical and economic challenges at process nodes as we push below 28nm, increasingly product groups are looking towards through-silicon-via (TSV) based approaches as a way of keeping Moore’s law… Read More

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An Approach to 20nm IC Design

An Approach to 20nm IC Design
by Daniel Payne on 07-17-2012 at 10:10 am
Categories: Cadence, EDA

Last month at DAC I learned how IBM, Cadence, ARM, GLOBALFOUNDRIES and Samsung approach the challenges of SoC design, EDA design and fabrication at the 20nm node. Today I followed up by reading a white paper on 20nm IC design challenges authored by Cadence, a welcome relief to the previous marketing mantra of EDA 360.

Here’s… Read More