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EDA

Electronic Design Automation

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Chip-Package-System Solution Center

Chip-Package-System Solution Center
by Paul McLellan on 08-14-2012 at 5:48 pm
Categories: Ansys, Inc., EDA

One of the really big changes about chip design is the way over the last decade or so it is no longer possible to design an SoC, a package for it to go in and the board for the package using different sets of tools and methodologies and then finally bond out the chip and solder it onto the board. The three systems, Chip-Package-System have… Read More

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Ajoy Bose and Hogan: SoC Realization

Ajoy Bose and Hogan: SoC Realization
by Paul McLellan on 08-13-2012 at 6:47 pm
Categories: EDA

Tomorrow night in Sunnyvale at the National Institute of Technology Alumni meeting, Ajoy Bose and Jim Hogan will talk about different aspects of SoC Realization. I’ve been saying for some time that design is changing and the block level is really where the action is. That is the right level to put together a virtual platform… Read More

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Interview with Brien Anderson, CAD Engineer

Interview with Brien Anderson, CAD Engineer
by Daniel Payne on 08-13-2012 at 11:15 am
Categories: Cliosoft, EDA

I first met Brien Anderson on LinkedIn because we share common groups and interests, so I decided to interview him and discover how CAD tools enabled IC design at Synpatics, a company with capacitive sensing technology used in smart phones, tablets and touch screens.… Read More

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A Brief History of SPICE

A Brief History of SPICE
by Daniel Payne on 08-10-2012 at 4:06 pm
Categories: EDA

SPICE is an acronym for Simulation Program with Integrated Circuit Emphasis and represents a class of EDA software used by circuit designers at the transistor-level to predict the timing, frequency, voltage, current or power of an IC or interconnect before fabrication.

In 1971 there was a tool called CANCER (Computer Analysis… Read More

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While you’re reading the SoC manual

While you’re reading the SoC manual
by Don Dingee on 08-09-2012 at 8:30 pm
Categories: EDA, IP, Siemens EDA

There was a day, not too long ago, when a software developer could be intimate with a processor through understanding its register set. Before coding, developers would reach for a manual, digging through pages and pages of 1s and 0s with defined functions to find how to gain control over the processor and its capability. One bit set… Read More

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A Brief History of EDA

A Brief History of EDA
by Daniel Nenni on 08-05-2012 at 6:00 pm
Categories: EDA

Electronic Design Automation, or more affectionately known as EDA, is a relatively young $5B industry with a very colorful upbringing, one that I have experienced firsthand, I’m very grateful for, and is an honor to write about. Today EDA employs an estimated 27,000 people! There is a nice EDA Wikipedia page which can be found here… Read More

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Synopsys Aquires Springsoft

Synopsys Aquires Springsoft
by Paul McLellan on 08-03-2012 at 12:07 pm
Categories: EDA, Synopsys

Today it was announced that Synopsys is acquiring SpringSoft for $406 million dollars ($12.2B Taiwanese). Coincidentally, I was in SpringSoft’s US office yesterday to talk about how Laker is being used for 20nm design. More of that later. But there was certainly nothing to indicate that anyone there was expecting this.… Read More

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Webinar on Multi-voltage/VT/Channel Length Libraries

Webinar on Multi-voltage/VT/Channel Length Libraries
by Daniel Payne on 08-02-2012 at 8:10 pm
Categories: EDA, Synopsys

ken brock

Ken Brockof Synopsys presented on how to optimize your SoC design for low power at 40nm, 28nm and 20nm nodes in a webinar today. Ken and I both worked together at Silicon Compilers back in the late 1980’s, the best EDA/IP company that I’ve had the pleasure to join.

The webinar made a brief mention of 14nm and FinFETS but … Read More

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Cadence Digital Flow

Cadence Digital Flow
by Paul McLellan on 08-01-2012 at 8:01 pm
Categories: Cadence, EDA

Cadence has a series of webinars about their digital flow, focused on 28nm design. It is easy for all of us in the EDA ecosystem to assume that everyone is already doing 20/22nm design, if not 14nm already. But in fact most designs are still being done at 45nm and 65nm; 28nm is still a big challenging step.

One of the tools in the Cadence… Read More