hip webinar automating integration workflow 800x100 (1)
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 3904
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 3904
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

Posted on

Cadence at 20nm

Cadence at 20nm
by Paul McLellan on 08-21-2012 at 8:10 pm
Categories: Cadence, EDA

Cadence has a new white paper out about the changes in IC design that are coming at 20nm. One thing is very clear: 20nm is not simply “more of the same”. All design, from basic standard cells up to huge SoCs has several new challenges to go along with all the old ones that we had at 45nm and 28nm.

I should emphasize that the paper… Read More

Posted on

A Brief History of ASIC, part I

A Brief History of ASIC, part I
by Paul McLellan on 08-21-2012 at 7:00 pm
Categories: EDA

In the early 1980s the ideas and infrastructure for what would eventually be called ASIC started to come together. Semiconductor technology had reached the point that a useful number of transistors could be put onto a chip. But unlike earlier, when a chip only held a few transistors and thus could be used to create basic generic building… Read More

Posted on

A Brief History of Mentor Graphics

A Brief History of Mentor Graphics
by Beth Martin on 08-20-2012 at 11:00 pm
Categories: EDA, Siemens EDA

In 1981, Pac-Man was sweeping the nation, the first space shuttle launched, and a small group of engineers in Oregon started not only a new company (Mentor Graphics), but an entirely new industry, electronic design automation (EDA).


Mentor founders Tom Bruggere, Gerry Langeler, and Dave Moffenbeier left Tektronix with a great… Read More

Posted on

MemCon 2012: Cadence and Denali

MemCon 2012: Cadence and Denali
by Eric Esteve on 08-20-2012 at 7:00 am
Categories: Cadence, EDA

I was very happy to see that Cadence has decided to hold MEMCON again in 2012, in Santa Clara on September 18[SUP]th[/SUP] . The session will start with “New Memory Technologies and Disruptions in the Ecosystem”from Martin Lund.

Martin is the recently (March this year) appointed Senior VP for the SoC Realization Group at cadence:… Read More

Posted on

A Brief History of SoCs

A Brief History of SoCs
by Daniel Nenni on 08-19-2012 at 10:00 am
Categories: EDA

Interesting to note; our cell phones today have more computing power than NASA had for the first landing on the moon. The insides of these mobile devices that we can’t live without are not like personal computers or even laptops with a traditional CPU (central processing unit) and a dozen other support chips. The brain, heart, and… Read More

Posted on

SystemVerilog from Nevada?

SystemVerilog from Nevada?
by Daniel Payne on 08-16-2012 at 10:58 am
Categories: Aldec, EDA

When I think of EDA companies the first geography that comes to mind is Silicon Valley because of the rich history of semiconductor design and fabrication, being close to your customers always makes sense. In the information era it shouldn’t matter so much where you develop EDA tools, so there has been a gradual shift to a wider… Read More

Posted on

40 Billion Smaller Things On The Clock

40 Billion Smaller Things On The Clock
by Don Dingee on 08-15-2012 at 8:00 pm
Categories: Cadence, EDA

Big processors get all the love, it seems. It’s natural, since they are highly complex beasts and need a lot of care and feeding in the EDA and fab cycle. But the law of large numbers is starting to shift energy in the direction of optimizing microcontrollers.

I mulled the math in my head for a while. In a world with 7 billion people and … Read More

Posted on

Chip-Package-System Solution Center

Chip-Package-System Solution Center
by Paul McLellan on 08-14-2012 at 5:48 pm
Categories: Ansys, Inc., EDA

One of the really big changes about chip design is the way over the last decade or so it is no longer possible to design an SoC, a package for it to go in and the board for the package using different sets of tools and methodologies and then finally bond out the chip and solder it onto the board. The three systems, Chip-Package-System have… Read More

Posted on

Ajoy Bose and Hogan: SoC Realization

Ajoy Bose and Hogan: SoC Realization
by Paul McLellan on 08-13-2012 at 6:47 pm
Categories: EDA

Tomorrow night in Sunnyvale at the National Institute of Technology Alumni meeting, Ajoy Bose and Jim Hogan will talk about different aspects of SoC Realization. I’ve been saying for some time that design is changing and the block level is really where the action is. That is the right level to put together a virtual platform… Read More

Posted on

Interview with Brien Anderson, CAD Engineer

Interview with Brien Anderson, CAD Engineer
by Daniel Payne on 08-13-2012 at 11:15 am
Categories: Cliosoft, EDA

I first met Brien Anderson on LinkedIn because we share common groups and interests, so I decided to interview him and discover how CAD tools enabled IC design at Synpatics, a company with capacitive sensing technology used in smart phones, tablets and touch screens.… Read More