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EDA

Electronic Design Automation

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IBM Tapes Out 14nm ARM Processor on Cadence Flow

IBM Tapes Out 14nm ARM Processor on Cadence Flow
by Paul McLellan on 10-30-2012 at 7:33 pm
Categories: Cadence, EDA

An announcement at the ARM conference was of a joint project to tape out an ARM Cortex-M0 in IBM’s 14nm FinFET process. In fact they taped out 3 different versions of the chip using different routing architectures to see the impact on yield.

This was the first 14nm ARM tapeout, it seems. I’m sure Intel has built plenty … Read More

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Improving FPGA Prototype Debugging

Improving FPGA Prototype Debugging
by Daniel Payne on 10-30-2012 at 10:00 am
Categories: EDA

FPGA Prototyping is growing in popularity as a method to get an SoC design into hardware running at clock speeds up to 100MHz or so. One downside during traditional FPGA prototyping debug is the limited number of internal signals that you can observe while trying to chase down bugs in the hardware design in the presence of running … Read More

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Jasper Property Synthesis Apps

Jasper Property Synthesis Apps
by Paul McLellan on 10-29-2012 at 7:00 am
Categories: EDA

Jasper restructured JasperGold so that it could deliver its formal technology more flexibly by having a base system and a porfolio of apps. This would also make it easier to upgrade capabilities by creating new apps. Today, Jasper announced two new apps:

  • JasperGold Structural Property Synthesis (SPS)
  • JasperGold Behavioral
… Read More
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An AMS Reference Flow for Power Management Designs

An AMS Reference Flow for Power Management Designs
by Daniel Payne on 10-26-2012 at 5:42 pm
Categories: Cadence, EDA

At DAC in June I visited and blogged about 30+ EDA and Semi IP companies, however I didn’t have time to watch the TowerJazz presentation in the Cadence Theater entitled: AMS Flow for Power Management Designs. Today I watched the 26 minute video and have summarized what I learned in this blog post.… Read More

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Simulation: Expert Insights into Modeling Microcontrollers @ Renesas DevCon

Simulation: Expert Insights into Modeling Microcontrollers @ Renesas DevCon
by Holly Stump on 10-25-2012 at 9:03 pm
Categories: EDA, Events, Synopsys

“Simulation: Expert Insights into Modeling Microcontrollers” was the recent panel hot topic at Renesas DevCon2012, featuring Paolo Giustoof GM, Mark Ramseyerof Renesas, Marc Serughettiof Synopsys, Jay Yantchevof ASTC / VWorks, and Simon Davidmannof Imperas.
… Read More

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SoC emulation syncs up with SuperSpeed USB

SoC emulation syncs up with SuperSpeed USB
by Don Dingee on 10-25-2012 at 9:00 pm
Categories: EDA, IP, Siemens EDA

They say what adds value is to take something difficult and make it look simple. USB looks so simple when it is done right, but designers know it can be one of the more tempermental features in an SoC, especially in the latest SuperSpeed incarnation.… Read More

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Brian Bailey Interviews Kathryn Kranen

Brian Bailey Interviews Kathryn Kranen
by Paul McLellan on 10-25-2012 at 6:23 pm
Categories: EDA

Brian Bailey at EETimes has an interesting interview with Kathryn Kranen. He says that the interview will be published in installments but the first one is up here. This first installment is mostly about how long-lived EDA companies (and others) have become since it takes a long time to build up enough revenue to be able to IPO.

She… Read More

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Model Driven Development

Model Driven Development
by Paul McLellan on 10-25-2012 at 5:50 pm
Categories: EDA, Siemens EDA

Mentor has a webinar on Model Driven Development (MDD) for Systems Engineering, presented by Bill Chown. It is actually the first of 15 webinars. This first one is just over 30 minutes long and I assume the others will be too. The webinar focuses on embedded system development, which historically has largely been validated using… Read More

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A Brief History of Semiconductors

A Brief History of Semiconductors
by Paul McLellan on 10-25-2012 at 3:00 pm
Categories: EDA

In the last few decades, electronics has become more and more central to our lives. When I was a child the only electronics in the house was the radio and the television, both of which contained tubes. Two big things happened that upended that world: the invention of the transistor and the invention of the integrated circuit. A modern… Read More

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CDNLive Call For Papers

CDNLive Call For Papers
by Paul McLellan on 10-24-2012 at 6:44 pm
Categories: Cadence, EDA

The Silicon Valley CDNLive, the Cadence user conference, will be on March 12-13th 2013 in Santa Clara. But the heart of CDNLive are customer presentations and the call for papers is now open. The deadline is December 4th (at 5pm PST for people who really like to come down to the wire). At this point only an abstract is required.

There… Read More