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Electronic Design Automation
At the 2010 DACI moderated a panel session on SPICE and Fast SPICE circuit simulation, and one of the panelists was PierLuigi Dagliofrom STMicroelectronics. To get an update on SPICE circuit simulation at ST I read a PDF document at Mentor titled: Improving the Quality of SPICE Simulation Results with Eldo Premier at ST.
ST does … Read More
In a shocking move TSMC now favors Cadence over Synopsys! Okay, not so shocking, especially after the Synopsys acquisitions of Magma, Ciranova, SpringSoft, and the resulting product consolidations. Not shocking to me at all since my day job is Strategic Foundry Relationships for emerging EDA, IP, and fabless companies.
Rick… Read More
Repeat after me: SoCs are paperweights if they can’t be programmed. Succeeding with a new part today means supporting a robust developer program to attract and engage as many creatives as possible. NVIDIA has teamed up with Mentor Graphics in just such an adventure. If you read just the press release, you may have missed the real … Read More
Mentor Graphics will be all over DVCon next week (February 25-28) at the DoubleTree hotel in San Jose.
In addition to attending all the panels, tutorials, posters, and the keynote, you can visit Mentor in booth 901 on the exhibit floor.
Here’s the lineup of Mentor-related events:… Read More
One of the privilages of blogging for SemiWiki is invitations to the top conferences around the world including the International Solid-State Circuits Conference (ISSCC) in San Francisco this week. Amazing, this conference is older than I am:
ISSCC 2013 is the 60th Conference in an incredibly long-lasting series. Following… Read More
For those of you who don’t know, Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification… Read More
You are going to be developing software for an SoC that contains an ARM Cortex-A57 64-bit CPU. Or perhaps it is an SoC containing ARM’s hybrid big.LITTLE multi-core architecture that combines one or more low power cores with some high power, high performance cores to get the best of both worlds: high throughput when it is needed… Read More
I read two blogs this week that got me to thinking about contingencies in SoC implementation. By contingency I mean using an EDA tool flow from the leading vendor for logic synthesis and then discovering that you cannot route the design without expanding the die size after a few weeks of concerted effort, then having to come up with… Read More
EDA tools come in all sizes and price ranges, so I was pleased to readthat Tanner EDAhas completed an integration with Incentia. A few months ago Tanner announced their integration with Aldec for digital simulation, and today’s announcement extends their tool suite to include digital synthesis and static timing. Here’s… Read More
Assertion Synthesis is a new tool for verification and design engineers that can be used with simulation or emulation. At DVCon Yuan Lu of Atrenta is presenting a tutorial on Atrenta’s BugScope along with John Henri Jr of Cadence explaining how it helps emulation and Baosheng Wang of AMD discussing their experiences of the… Read More
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