In previous design generations interconnect could safely be modeled by extraction using just R and C values. Parasitics in interconnect are important because they can affect the operating frequency or phase error in circuits like VCO’s. The need to model parasitics properly in wires is just as applicable in PA’s, LNA’s and for… Read More
Electronic Design Automation
Locked on FPGA design brand recognition
Back in the days where computing was dominated by a few big (and now mostly dearly departed) names, there was a saying: “Nobody ever got fired for buying IBM.” The relative safety of immediate brand recognition, especially among non-technical upper management, dissuaded many users from recommending or even seeking out other … Read More
Synopsys’s Next Generation Emulator, ZeBu Server-3
Since Synopsys acquired Eve over a year ago, they haven’t announced anything new in the ZeBu product line. Emulators are not like software where you expect incremental releases a couple of times per year, each new “release” is a complete re-design using new hardware fabric in a new process technology. Earlier… Read More
Mixed-Signal SoC Debugging & IP Integration Made Easy
A semiconductor SoC design can have multiple components at different levels of abstractions from different sources and in different languages. While designing an SoC, IPs at different levels have to be integrated without losing the overall design goals. Of course, quality of an IP inside and outside of an SoC must be tested thoroughly.… Read More
IoT: the sum of all technology opportunities
There was a time not that long ago, before smartphones arrived on the scene, where Mentor Embedded Nucleus RTOS was dominant in non-Nokia feature phones – Mentor is part of the “Billion Unit Mobile Club”. Since then, Mentor has been searching to recreate that type of success, and like so many other software firms, they are now aiming… Read More
TI’s Way of Strategies – Formation & Execution
For a company to stand still and continually prosper even after facing several downturns in its career of 80+ years, and still move swiftly with strong commitment and confidence, its strategy has to be right and rock solid possessing sustainable competitive advantage, and of course it has to be an early mover in everything it does… Read More
A Brief History of Chip Design at Apple Computer
Steve Wozniak in 1976 designed the Apple 1 while working at HP during the daytime, and he used standard parts to keep costs low, like:
- 6502 CPU from MOS Technology
- 8K of DRAM
- TTL logic for driving video and random logic
- PROM to hold the BASIC language and primitive OS
SoC Functional Verification Planning and Management Goes Big
Big SoC designs typically break existing EDA tools and old methodologies, which then give rise to new EDA tools and methodologies out of necessity. Such is the case with the daunting task of verification planning and management where terabytes of data have simply swamped older EDA tools, making them unpleasant and ineffective… Read More
A Methodology for Assertion Reuse in SoC Designs
As your SoC design can contain hundreds of IP blocks, how do you verify that all of the IP blocks will still work together correctly once assembled? Well, you could run lots of functional verification at the full-chip level and hope for the best in terms of code coverage and expected behavior. You could buy an expensive emulator to … Read More
6 reasons Synopsys covets C/C++ static analysis
By now, you’ve probably seen the news on Synopsys acquiring Coverity, and a few thoughts from our own Paul McLellan and Daniel Payne in commentary, who I respect deeply – and I’m guessing there are many like them out there in the EDA community scratching their heads a little or a lot at this. I’m not from corporate, but I am here… Read More
CES 2026 and all things Cycling