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EDA

Electronic Design Automation

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Jasper at DVCon and EJUG

Jasper at DVCon and EJUG
by Paul McLellan on 03-13-2014 at 7:05 pm
Categories: EDA

The Jasper European User Group meeting (EJUG) is coming up in a couple of weeks. It will be held in the Munich Hilton (which I have stayed in many times, the S-bahn from the airport pretty much stops in the basement) on April 2nd.

The schedule for the day is:
9:00 AM – Registration and continental breakfast
9:30 AM – Jasper… Read More

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Cadence and ARM BFF

Cadence and ARM BFF
by Paul McLellan on 03-13-2014 at 6:38 pm
Categories: Arm, Cadence, EDA, IP

The biggest market for semiconductors is mobile and an ARM processor is the center of the axle around which it revolves. So everyone in the mobile ecosystem needs to work closely with ARM. At CDNLive earlier this week Cadence and ARM announced that they are deepening their partnership. Most of what they announced makes it a lot easier… Read More

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Designing for Wearables!

Designing for Wearables!
by Daniel Nenni on 03-13-2014 at 5:30 pm
Categories: EDA, Tanner EDA

Wearables are going to be a real game changer for the fabless semiconductor ecosystem, absolutely. What other high volume semiconductor market segment has such a low barrier of entry? Speaking of low barrier of entry, the first stop on my Southern California trip last week was Monrovia, the home of Tanner EDA. Tanner is already … Read More

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Mark your Date for Semiconductor Design Vision

Mark your Date for Semiconductor Design Vision
by Pawan Fangaria on 03-13-2014 at 4:30 am
Categories: Concept Engineering, EDA

A very popular acronym is ‘WYSIWYG’ – What You See Is What You Get! This is very true and is important to visualize things to make it better in various aspects such as aesthetics, compactness, organization, structure, understandable for correction and so on; the most important, in case of semiconductor design, is being able to identify… Read More

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A Tool Conceived With Designers’ Input and Developed from Scratch

A Tool Conceived With Designers’ Input and Developed from Scratch
by Pawan Fangaria on 03-12-2014 at 10:15 am
Categories: EDA

If we look at the past, most of the EDA tools in the semiconductor design space have originated from a designers’ need to do things faster. Regardless of whether it is design exploration, manual design, simulation, verification, optimization (Power Performance Area – PPA) and many other steps in the overall design flow.… Read More

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Now even I can spot bad UVM

Now even I can spot bad UVM
by Don Dingee on 03-11-2014 at 8:30 pm
Categories: Aldec, EDA

Most programmers can read a code snippet and spot errors, given enough hours in the day, sufficient caffeine, and the right lens prescription. As lines of code run rampant, with more unfamiliar third-party code in the mix, interprocedural and data flow issues become more important – and harder to spot.

Verification IP particularly… Read More

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Effective Verification Coverage through UVM & MDV

Effective Verification Coverage through UVM & MDV
by Pawan Fangaria on 03-10-2014 at 5:00 pm
Categories: Cadence, EDA

In the current semiconductor design landscape, the design size and complexity of SoCs has grown to large extent with stable tools and technologies that can take care of integrating several IPs together. With that mammoth growth in designs, verification flows are evolving continuously to tackle the verification challenges … Read More

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WordPress and EDA Software, How Do They Compare?

WordPress and EDA Software, How Do They Compare?
by Daniel Payne on 03-09-2014 at 8:34 pm
Categories: EDA

I first started using WordPress in 2008 after having written my own Content Management System (CMS) to build and manage web sites. WordPress is the number one CMS in the world, is just 10 years old, and is used by over 70 million users. What got me thinking about WordPress and EDA software companies was a recent book by Scott Burken, … Read More

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Semiconductor Strategy – From Productivity to Profitability

Semiconductor Strategy – From Productivity to Profitability
by Pawan Fangaria on 03-08-2014 at 8:30 am
Categories: Dassault Systemes, EDA

The semiconductor industry seems to be the most challenged in terms of cost of error; a delay of 3 months in product development cycle can reduce revenue by about 27% and that of 6 months can reduce it by almost half; competition is rife, pushing the products to next generation (with more functionality, low power, high performance,… Read More

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IC Layout with Interactive or Batch DRC and LVS Results

IC Layout with Interactive or Batch DRC and LVS Results
by Daniel Payne on 03-07-2014 at 6:27 pm
Categories: EDA

IC designers have a long tradition of mixing and matching EDA tools from multiple vendors, mostly because they enjoy best-in-class tools, or they just purchased each EDA tool at a different time and asked for them to work together. Such is this case with IC layout tools from Silvacoand DRC/LVS tools from Mentor Graphics. Pawan Fangaria… Read More