Banner Electrical Verification The invisible bottleneck in IC design updated 1
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EDA

Electronic Design Automation

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TSMC OIP presentations available!

TSMC OIP presentations available!
by Beth Martin on 01-27-2014 at 6:27 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

Are you a TSMC customer or partner? If so, you’ll want to take a look at these presentations from the 2013 TSMC Open Innovation Platform conference:

… Read More
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Simulation of Novel TFT Devices

Simulation of Novel TFT Devices
by admin on 01-27-2014 at 5:45 pm
Categories: EDA

Traditionally logic devices built on top of thin-film-transistors (TFTs) have used one type of device, either an NMOS a-Si: TFT (hydrogenated amorphous silicon) or a PMOS organic device. Recently a-Si:H and pentacene PMOS TFTs have been integrated into complementary logic structures similar to CMOS. This, in turn, creates… Read More

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What will drive MEMS to drive I-o-T and I-o-P?

What will drive MEMS to drive I-o-T and I-o-P?
by Pawan Fangaria on 01-27-2014 at 5:45 am
Categories: Coventor, EDA, GlobalFoundries, STMicroelectronics

By I-o-P, I mean Internet-of-People- I couldn’t think of anything better than this to describe a technology which becomes your custodian for everything you do; you may consider it as your good companion through life or an invariably controlling spy. This is obvious with the embedded sensor techno-products such as Kolibree, a … Read More

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SPICE Circuit Simulator Gets a Jolt

SPICE Circuit Simulator Gets a Jolt
by Daniel Payne on 01-25-2014 at 11:28 am
Categories: EDA

I’ve been using SPICE circuit simulators since 1978, both internally and commercially developed, and a lot has changed since the early days where netlists were simulated in batch mode on time-share mainframes. We used to wait overnight for our simulations to complete, and in the morning had to pickup our output results … Read More

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Stop TDDB from getting through peanut butter

Stop TDDB from getting through peanut butter
by Don Dingee on 01-24-2014 at 6:00 pm
Categories: EDA, Siemens EDA

There are a few dozen causes of semiconductor failure. Most can be lumped into one of three categories: material defects, process or workmanship issues, or environmental or operational overstress. Even when all those causes are carefully mitigated, one factor is limiting reliability more as geometries shrink – and it… Read More

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Parasitic Debugging in Complex Design – How Easy?

Parasitic Debugging in Complex Design – How Easy?
by Pawan Fangaria on 01-23-2014 at 9:00 am
Categories: Concept Engineering, EDA

When we talk about parasitic, we talk about post layout design further expanded in terms of electrical components such as resistances and capacitances. In the semiconductor design environment where multiple parts of a design from different sources are assembled together into highly complex, high density SoC, imagine how complex… Read More

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ESD at TSMC: IP Providers Will Need to Use Mentor to Check

ESD at TSMC: IP Providers Will Need to Use Mentor to Check
by Paul McLellan on 01-22-2014 at 1:24 pm
Categories: EDA, Foundries, TSMC

I met with Tom Quan of TSMC and Michael Beuler-Garcia of Mentor last week. Weirdly, Mentor’s newish buildings are the old Avant! buildings where I worked for a few weeks after selling Compass Design Automation to them. Odd sort of déja vu. Historically, TSMC has operated with EDA companies in a fairly structured way: TSMC … Read More

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Have you Tried ALDEC?

Have you Tried ALDEC?
by Luke Miller on 01-22-2014 at 1:00 pm
Categories: Aldec, EDA

I must admit. I was too comfortable. Let me explain, I’m a ModelSim guy from Mentor Graphics. I did not really think nor care much of the other RTL simulator options. How could someone build a better tool with respect to simulation? Let me introduce you to Aldec. Aldec was founded in 1984 by Dr. Stanley M. Hyduke. 30 years later they are… Read More

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Just Released! Fabless: The Transformation of the Semiconductor Industry

Just Released! Fabless: The Transformation of the Semiconductor Industry
by Daniel Nenni on 01-22-2014 at 12:00 pm
Categories: EDA, Foundries, IP

The book “Fabless: The Transformation of the Semiconductor Industry” is now available in the Kindle (mobi) and iBooks (ePub) formats. We are really looking forward to your feedback before we go to print in March. This was truly a Tom Sawyer experience for me. As the story goes Tom made whitewashing a fence seem like fun so his friends… Read More

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A Power Optimization Flow at the RTL Design Stage

A Power Optimization Flow at the RTL Design Stage
by Daniel Payne on 01-21-2014 at 10:20 pm
Categories: EDA

SoC designers can code RTL, run logic synthesis, perform place and route, extract the interconnect, then simulate to measure power values. Though this approach is very accurate, it’s also very late in the implementation flow to start thinking about how to actually optimize a design for the lowest power while meeting all… Read More