SiC 800 2026ChipletSummit Static (1)
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EDA

Electronic Design Automation

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Evaluate MEMS Devices out-of-fab Before Fabrication

Evaluate MEMS Devices out-of-fab Before Fabrication
by Pawan Fangaria on 03-21-2014 at 10:30 am
Categories: Coventor, EDA

MEMS design and fabrication is highly complex in the sense that the fabrication process heavily depends on the design, unlike IC fabrication which has a standard set of processes. A slight change in MEMS design can alter its fabrication steps to a large extent. For example, setting device parameters such as capacitance or linear… Read More

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ARM, Cadence and the Internet of Things

ARM, Cadence and the Internet of Things
by Paul McLellan on 03-20-2014 at 6:30 pm
Categories: Arm, Cadence, EDA, IP

There is clearly a lot of hype about the Internet of Things (IoT) right now, but also it is clear that it will be a real market. In fact, it already is with various medical, fitness and home-appliance products already available. At CES in January, wearables was probably the biggest trend. That doesn’t always pan out (3D TV was… Read More

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TLM Modeling Environment Goes Commercial

TLM Modeling Environment Goes Commercial
by Daniel Payne on 03-20-2014 at 6:00 pm
Categories: EDA, Magillem, STMicroelectronics

The most successful EDA companies typically choose a domain where they have deep knowledge, then serve a few leading-edge customers that are willing to work with a start-up in exchange for early access to that new technology. The theory is that if you can satisfy the leading-edge customer then you can also satisfy the rest of the … Read More

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Triple Patterning

Triple Patterning
by Paul McLellan on 03-19-2014 at 1:00 pm
Categories: EDA, Foundries

As you can’t have failed to notice by now, 28nm is the last process node that does not require double patterning. At 20nm and below, at least some layers require double patterning. The tightest spacing is typically not the transistors but the local interconnect and, sometimes, metal 1.


In the litho world they call double patterning… Read More

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Aldec the leader in DO254

Aldec the leader in DO254
by Luke Miller on 03-19-2014 at 12:00 pm
Categories: Aldec, EDA, FPGA, Xilinx

I am convinced after studying out the matter, that Aldec is one of the leaders in DO254 certification. As you listen and read the news as I do about flight MA-370, you keep theorizing and wondering. This is a good time to introduce the reader to the seriousness of flight worthy electronics and the arduous process to achieve certification.… Read More

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Social Media at Carbon Design Systems

Social Media at Carbon Design Systems
by Daniel Payne on 03-18-2014 at 11:12 am
Categories: EDA

Started in 2002 Carbon Design Systems has ESL (Electronic System Level) modeling and validation tools for complex SoC design. With their software you can:

  • Perform system level model generation of existing and 3rd party IP directly from RTL for use in any virtual platform
  • Do performance analysis & optimization of SoC architectures
… Read More
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Mentor U2U Is On April 10th

Mentor U2U Is On April 10th
by Paul McLellan on 03-17-2014 at 7:19 pm
Categories: EDA, Siemens EDA

If you are a Mentor user, U2U, the Mentor User group is coming up on April 10th. This is an all day event at the DoubleTree. The event is free. Registration starts at 8am and the agenda itself starts at 9am. There is a reception from 5-6pm in the evening.

There are three keynotes. At 9am: Wally Rhines, CEO of Mentor. The Big Squeeze. For … Read More

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A Fill Solution for 20nm at TSMC

A Fill Solution for 20nm at TSMC
by glforte on 03-17-2014 at 5:12 pm
Categories: EDA, Siemens EDA

By Jeff Wilson, Mentor Graphics

We’ve talked about the new requirements for Fill in IC design for advanced nodes in previous blogs on this site. This time I’d like describe the fill solution that Mentor and TSMC have jointly developed to meet the requirements of fill for TSMC’s 20nm (N20) manufacturing process.

The traditional… Read More

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Xilinx & Apache Team up for FPGA Reliability at 20nm

Xilinx & Apache Team up for FPGA Reliability at 20nm
by Pawan Fangaria on 03-17-2014 at 12:00 am
Categories: Ansys, Inc., EDA, FPGA, Xilinx

In this age of SoCs with hundreds of IPs from different sources integrated together and working at high operating frequencies, FPGA designers are hard pressed keeping up the chip reliability from issues arising out of excessive static & dynamic IR drop, power & ground noise, electro migration and so on. While the IPs are… Read More

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Cadence is all about Semiconductor IP!

Cadence is all about Semiconductor IP!
by Daniel Nenni on 03-16-2014 at 9:00 am
Categories: Cadence, EDA

Cadence continues on its quest to be a top semiconductor IP supplier which is a good thing since the semiconductor world now revolves around IP. Cadence CEO Lip-Bu Tan mentioned IP 14 times during his keynote and he was followed by the president of Imagination Technologies and the CEO of recently acquired Tensilica. I was not afforded… Read More