SiC Forum2025 8 Static v3
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Palladium’s Little Brother Protium

Palladium’s Little Brother Protium
by Paul McLellan on 07-17-2014 at 8:00 am

Today, Cadence announced Protium, a new FPGA prototyping platform for software development. During development of an SoC, the most appropriate methodology changes. In the early days, developing RTL, the primary tool is simulation. Then, as the blocks get bigger or as the whole chip starts to come together, typically simulation… Read More


Catching IC Manufacturing Defects With Slack-Based Transition Delay Testing

Catching IC Manufacturing Defects With Slack-Based Transition Delay Testing
by Daniel Payne on 07-16-2014 at 3:00 pm

Test engineers are often the unsung heroes in the semiconductor world, because they have the tough job of deciding if each IC is good or bad, while taking the least amount of time on a tester and ensuring that the tests are actually finding and uncovering all manufacturing and process variation defects. Simple stuck-at fault models… Read More


Cadence Announces Quantus Next Generation Extraction

Cadence Announces Quantus Next Generation Extraction
by Paul McLellan on 07-14-2014 at 7:00 pm

Today Cadence announced their next generation extraction solution called Quantus QRC. Actually they are technically announcing it tomorrow, since it is being announced at CDNLive in Korea where it is already Tuesday morning.

As with the other recently announced tools that end in -us, Tempus (timing signoff) and Voltus (power… Read More


Paving the Path for Robust Electronic System Design

Paving the Path for Robust Electronic System Design
by Pawan Fangaria on 07-13-2014 at 7:30 pm

In today’s era of low power and high performance components, preferably on a single chip provides impetus to much larger electronic systems packaged into much smaller cases; smartphones are the immediate examples which encapsulate multiple functions other than the intended ones, viz. phone and data communication. As an example,… Read More


EDA Mergers & Acquisitions Wiki Now Includes IP

EDA Mergers & Acquisitions Wiki Now Includes IP
by Ian Getreu on 07-10-2014 at 4:00 pm

When I started collecting my list of EDA mergers and acquisitions about 30 years ago, my objective was simply to determine the number of logos each EDA company owns. For that reason, I collected all the fish-eat-fish-eat-fish…. mergers and acquisitions, going way back to the very early days of EDA (even before it was called EDA).… Read More


Modeling and Analysis of Single Event Effects (SEE)

Modeling and Analysis of Single Event Effects (SEE)
by Daniel Payne on 07-08-2014 at 4:00 pm

Single Event Effects (SEE) are important because we depend upon our consumer, industrial and aerospace products to work reliably. Protons, electrons, neutrons, or alpha particles may perturb the MOS or bipolar device operation in either a destructive or non-destructive fashion. Galactic cosmic rays are one source of these… Read More


S-engine Moves up the Integration of IPs into SoCs

S-engine Moves up the Integration of IPs into SoCs
by Pawan Fangaria on 07-07-2014 at 8:30 am

As the semiconductor design community is seeing higher and higher levels of abstraction with standard IPs and other complex, customized IPs and sub-systems integrated together at the system level, sooner than later we will find SoCs to be just assemblies of numerous IPs selected off-the-self according to the design needs and… Read More


Coventor Brings More Accuracy & Performance into Design of MEMS Devices

Coventor Brings More Accuracy & Performance into Design of MEMS Devices
by Pawan Fangaria on 07-06-2014 at 9:00 am

Although MEMS devices in various forms are now found in most electronic devices, predominantly in mobile, automotive, aerospace and many other applications, their major revolution, I believe, is yet to happen. We are seeing rapid innovation in MEMS reflected by their improvements in precision, performance, size reduction,… Read More


An Approach to Clock Domain Crossing for SoC Designs

An Approach to Clock Domain Crossing for SoC Designs
by Daniel Payne on 07-06-2014 at 12:20 am

Blogger Pawan Fangaria wrote about Clock Domain Crossing(CDC) a few weeks ago, and so I followed up tonight and watched a webinarabout CDC presented by Ravindra Anejaof Atrenta. An RTL design engineer would ultimately want a CDC verification tool that offers:

  • Fast throughput and thoroughness
  • Ability to debug and fix the source
Read More

In Case You Missed #51DAC

In Case You Missed #51DAC
by Daniel Nenni on 07-02-2014 at 9:50 am

This will probably end up being the most memorable DAC for us since Paul and I signed hundreds of copies of our book “Fabless: The Transformation of the Semiconductor Industry”. I’m not sure how we are going to top that next year but I’m confident we will think of something. If you want to catch up on the live blogs from the last three conferences… Read More