There has been a lot written on this topic, and some expensive tools proposed to solve this issue, but it is still a concern and a mystery for many designers. The point is that whatever efforts you do, the substrate is common to an entire chip and can cause some undesired coupling if not managed properly and at an early stage. As a start point, we can state that any block in a chip can inject current in the substrate, either through capacitive coupling from metal lines or from wells or through parasitic devices such as bipolar transistors if a PN junction is forward biased.
All the currents that are injected in the substrate combine through an impedance network that has one pin per injection point. As a result, each injection point, instead of having a quiet voltage, has some “noise” resulting from its own activity but also from the activity of other blocks/devices. And since each block exhibits some sensitivity to the noise on its substrate, the overall circuit may fail to reach target performance.
It is easy to have substrate pin for every block in a circuit. You just have to connect all the devices or wells diodes substrate pins to a dedicated substrate net/pin instead of a global. The point is to choose the right granularity. My advice at that point is that a coarse grain is much better that nothing and can always be refined later on as needed.
The hard point is to get the impedance network to connect all the substrate pins. Again, an approximate network is much better than nothing. A detailed analysis I could write about in another post shows that most series resistance to a substrate tie is located close to the tie. This is the reason why substrate ties are usually grouped in long lines and why in many process one has to put substrate ties every some distance. If this is done properly, the substrate inside a cell can be considered as a constant voltage area AT THE SILICON SURFACE. Of course, as you go deeper in silicon, things change.
Then,as a first approximation one can consider there is one access to the substrate per cell. As a start point, one can consider only the top level cells or those that are far enough from others. For many analog and mixed signal chips, the number of cells at that point is rather small, some tens at most. I used my home made 3D Field solver “EZMod3D” to perform the substrate equivalent schematic extraction. Here is an example for a small mixed signal chip I designed a while ago:
On this picture, one can see the 11 top level blocks, 1 being digital, 4 being noisy analog and 6 being sensitive analog. The blocks are described as constant voltage limits on top. The substrate has been described as a low resistivity P+ thick layer at the bottom and a higher resistivity epitaxial P- thin layer on top. The data for these layers were available in the process design manual. No need to create complicated tech files, just enter the physical characteristics of layers.
N nodes connect by N*(N-1)/2 impedances. For N=11, 11*(11-1)/2=55 Impedances
Considering resistivity values, permittivity values and operating frequencies, in this case, impedances appear to simplify simplify to resistances. EZMod3D will automatically set all the limits but one to GND, drive the non GND one with a voltage source, simulate that structure and extract all the currents in all the GND pins. This allows computing the N-1 impedances between the non GND pin and all the GND pins. Then moving around the non GND pin in N-1 simulations gives the whole picture and the equivalent netlist can be created.
I had to run the extraction again for the purpose of getting figures to write that post. EZMod3D required 40 Mbytes memory to run and completed in about one hour and a half on a 4 years old core i7 laptop. It issued directly the following netlist:
R1130 Node2 Node3 1.02408199664998670e+001
R2130 Node2 Node4 2.17593122679717650e+001
R3130 Node2 Node5 1.62515077027132730e+001
R4130 Node2 Node6 8.51530376823227900e+000
R5130 Node2 Node7 2.62288581224144860e+001
R6130 Node2 Node8 2.52566606961607540e+001
R7130 Node2 Node9 6.66757628924332550e+001
R8130 Node2 Node10 1.13673924166039660e+001
R9130 Node2 Node11 3.30231595959797420e+001
R10130 Node2 Node12 2.56098355567696920e+001
R2131 Node3 Node4 1.48623723718801100e+001
R3131 Node3 Node5 1.13061579624792760e+001
R4131 Node3 Node6 7.77357320381043330e+000
R5131 Node3 Node7 1.98342928529872720e+001
R6131 Node3 Node8 1.88483495757762750e+001
R7131 Node3 Node9 6.07654417616208920e+001
R8131 Node3 Node10 9.92209211715984910e+000
R9131 Node3 Node11 2.57862772544557010e+001
R10131 Node3 Node12 2.02746422406297140e+001
No need to go further here, there is no added value in reading this stuff!
At the time I designed the chip, the netlist could be simulated together with the circuit schematic and the package equivalent schematic, connecting the substrate pins of the cells to the substrate schematic and connecting the package pins appropriately. The simulation showed a number of issues that were not visible without substrate coupling. In particular, some fast current pulses resulting from simultaneous conduction in large CMOS inverters did couple through and caused undesired signals in the quite area. Usually when you face a substrate coupling issue you have to reduce the amplitude of disturbing signal through all possible design techniques, reduce the sensitivity of the disturbed cell and reduce coupling through substrate by a couple of technique I may detail in another post.
In the example case I decided to use two substrate zones, with two separate pads and package pins. EZMod3D predicted 6 ohms resistance between the two substrate zones. Together with 0.5 ohms for bonding, this approach improved substrate coupling by more than 20 dB. When the samples came in, one of the first measurements I did was the resistance between the two substrate pins. The measured value was 7 ohms. Pretty good agreement showing the validity of assumptions. And the coupling between noisy and quiet cells met the specification. Since that time, I have simulated substrate coupling for many chips and that often helped me optimizing the floorplan before any layout was done, saving lots of manpower and probably some runs.