Most analog cells have a power off mode intended to reduce power consumption. In this mode, all the circuit branches between the supply lines are set in a high impedance mode by driving MOS gates to a blocking voltage. This is a somewhat similar situation to that in tri-state digital circuits.
When a branch is set in that high impedance… Read More
Most analog designers are aware of loops stability. In most cases, stability is understood as AC stability, the goal is ensuring enough phase (gain) margin so as to avoid the loop to enter oscillation. But prior to studying AC stability, DC stability should be questioned. What is that DC stability only few people think of?… Read More
There has been a lot written on this topic, and some expensive tools proposed to solve this issue, but it is still a concern and a mystery for many designers. The point is that whatever efforts you do, the substrate is common to an entire chip and can cause some undesired coupling if not managed properly and at an early stage. As a start… Read More