hip webinar automating integration workflow 800x100 (1)
WP_Term Object
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 3899
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 3899
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0

Do you check your circuit DC stability?

Do you check your circuit DC stability?
by Jean-Francois Debroux on 08-26-2014 at 8:00 pm

Most analog designers are aware of loops stability. In most cases, stability is understood as AC stability, the goal is ensuring enough phase (gain) margin so as to avoid the loop to enter oscillation. But prior to studying AC stability, DC stability should be questioned. What is that DC stability only few people think of?

Let’s start with a very basic example: Let’s build a chain of two CMOS inverters, sweep input voltage from 0 to VDD (1.2 V here) and plot voltages at input, outputs of first and second inverter versus input voltage. We should get something like this:

Blue line is input, red line is first inverter output and yellow line is second inverter output.
Now, what if we connect output of second inverter to input of first? Obviously, we force input voltage to be equal to output voltage. Then possible operating points are all the points for which the blue and yellow lines above cross each other. These points are figured in the following graph where intermediate line has been removed for the sake of clarity:

For that circuit, the lines cross each other 3 times, at points 1, 2 and 3 as indicated by arrows on the graph. This circuit exhibits 3 possible operating points. Now, as every one knows, this circuit has two stable operating points, namely 1 and 3. Operating point 2 is not DC stable (even though it is the one a simulator gives as the result of a .OP command !). How can we say point 2 is not DC stable ?

The reason is that loop gain is >1 around point 2. If by chance the circuit falls in that state, any noise will push it away either towards point 1 or towards point 2. The reason for that is that output changes in the same direction as input but with a larger amplitude than input. Note that around points 1 and 2, loop gain is <1, these points are stable. So, there is no point in wondering about AC stability for this circuit. Points 1 and 3 have loop gain 1 but circuit will not stay in that state so it won’t oscillate around that point.

Now let’s consider a so called PTAT bias cell (which is actually PTAT/R if Widlar mirror is implemented with bipolar transistors). That cell is built from two current mirrors, one straight and one Widlar type, the output of one feeding the input of the other one. The transfer characteristics of the straight current mirror is a straight line with slope = 1. The Widlar mirror transfer characteristics is a curve with a slope >1 at the origin and a slope <1 at large currents. If we break the loop, force a current in one of the mirrors and plot input current and output of second mirror:

In blue, input current and in red output current. Obviously, when the loop is closed, input and output currents are equal, so an operating point exists each time the two lines cross each other.

Target operating point is where the two lines cross each other around 35 uA. At that point, loop gain is <1. This is why you never add frequency compensation to a PTAT bias. It is DC stable and loop gain is insufficient to enter in oscillation.
Around origin, things are more tricky: Depending on leakage currents and because of continuity around 0, several situations may occur. Both lines have about zero slope at negative currents. It is impossible to predict whether output current will increase more or less than input current right at the origin and this may be different from part to part. There are usually two operating points close to the origin, one being stable, the other one unstable. The stable one, actual or potential is the reason for adding a kickoff circuit to PTAT bias cell.

Finally, let’s consider an opamp used as a non inverting amplifier. If we break the loop, sweep inverting input voltage and look at divider bridge output, we notice a large, negative slope around amplifier offset voltage. In this case, loop gain is negative. As it is <1, this operating point is DC stable. And since the gain magnitude is larger than 1, the AC stability is questionable.

So, the criterion for DC stability is checking the loop gain with respect to +1. A value above +1 denotes a DC unstable operating point. A value below +1 denotes a DC stable operating point. A value below -1 can be AC unstable and has to be AC checked. Most circuits have one operating point. Some circuits, mainly loops have three. I once designed a circuit with cascode and boostrap that exhibited five, three being close to each other. Out of these three, one was the target and was DC stable, one was unstable, but the third one was undesired and was stable. It had to be removed by added circuitry.

Loops multiple operating points can be checked using the suggested method: Breaking the loop, sweeping input through the full possible range and plot input and output versus input. As in one of the examples, loops can be voltage mode or current mode.

Share this post via:


There are no comments yet.

You must register or log in to view/post comments.