Webinar PQC SemiwikiV4
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EDA

Electronic Design Automation

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Sequential Equivalence Checking with Jasper

Sequential Equivalence Checking with Jasper
by Paul McLellan on 10-01-2013 at 6:15 pm
Categories: EDA

When new restaurants open they sometimes have what is called a ‘soft opening’ where they open a few days earlier than the official opening night. They are less busy since nobody knows they are open yet, maybe the whole menu isn’t available and expectations may be lower. Of course, Broadway productions also often… Read More

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ST Endorses PowerArtist with ARM Cores & FDSOI libs

ST Endorses PowerArtist with ARM Cores & FDSOI libs
by Pawan Fangaria on 10-01-2013 at 12:00 pm
Categories: Ansys, Inc., EDA

It was an interesting webinar I attended, presented by STMicroelectronicson how they are benefited in power saving and thermal dissipation by using FDSOI technology and also by using PowerArtist in their design. So, it’s an advantage from both sides – semiconductor technology and semiconductor design tool. It’s worth attending… Read More

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Stick to the script for repeatable FPGA-based prototyping

Stick to the script for repeatable FPGA-based prototyping
by Don Dingee on 09-30-2013 at 7:00 pm
Categories: EDA, Synopsys

70% of today’s ASIC and SoC designs are being prototyped on FPGAs. Everybody knows that. But, did you know that automating the process of converting what could be thousands of ASIC “golden” files into FPGA-friendly versions can mean big savings in a large design?… Read More

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How to Quickly Optimize BEOL Process at Your Desk?

How to Quickly Optimize BEOL Process at Your Desk?
by Pawan Fangaria on 09-30-2013 at 11:00 am
Categories: Coventor, EDA

Engineers are always looking to improve the efficiency of how they work, but don’t want to sacrifice accuracy in the process. This is true in the world of semiconductor process development, where traditional build-and-test cycles are both time and resource intensive. But what if there was a way to do certain steps in a ‘virtual’… Read More

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With SCE-MI, timing really is everything

With SCE-MI, timing really is everything
by Don Dingee on 09-28-2013 at 11:00 pm
Categories: Aldec, EDA

In one of my favorite movies, Brad Pitt utters the only question that matters in baseball or technology management in the face of uncertainty: “Okay, good. What’s the problem?” Not surprisingly in that scene, as the question circles the table of experts used to doing things the old way, not a single one can answer it correctly in the… Read More

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TSMC Open Innovation Platform Forum, October 1st

TSMC Open Innovation Platform Forum, October 1st
by Paul McLellan on 09-28-2013 at 5:00 am
Categories: EDA, Foundries, IP, TSMC

One of TSMC’s two big Silicon Valley events each year is the Open Innovation Platform (OIP) Forum. This year it is on Tuesday October 1st. It is in the San Jose Convention Center and starts at 9am (registration opens at 8am). Pre-registration to attend is now open here or click on the image to the right.

From 9.10 to 9.40 is the … Read More

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What Mentor Said at ITC

What Mentor Said at ITC
by Beth Martin on 09-26-2013 at 4:47 pm
Categories: EDA

At the ITC test conference in early September, Mentor made three announcements. ITC is a big event for Mentor’s test group, and where they usually roll out their new tools and capabilities. The indefatigable Steve Pateras was captured on film describing them.

I’ve summarize Mentor’s three announcements and added… Read More

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SystemVerilog Assertions and Functional Coverage

SystemVerilog Assertions and Functional Coverage
by Daniel Payne on 09-24-2013 at 8:26 pm
Categories: EDA

Ashok Mehtahas designed processors at DEC and Intel, managed ASIC vendor relationships, verified networks SoCs, directed engineers at AMCC, and used SystemVerilog since it’s inception. He recently authored a book: SystemVerilog Assertions and Functional Coverage. The book is available in both hardcover and Kindle… Read More

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But I Never Have Seen a Synchronizer Failure

But I Never Have Seen a Synchronizer Failure
by Jerry Cox on 09-24-2013 at 8:00 am
Categories: EDA

You may say, “Why should I worry about synchronizer failures when I have never seen one fail in a product?” Perhaps you feel that the dual-rank synchronizer used by many designers makes your design safe. Furthermore, those chips that have occasional unexpected failures never show any forensic evidence of synchronizer failures.… Read More

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A Brief History of Silvaco

A Brief History of Silvaco
by Daniel Nenni on 09-23-2013 at 5:00 pm
Categories: EDA, Silvaco

Silvaco is the leading supplier of TCAD software, and a major supplier of EDA software for circuit simulation and design of analog, mixed-signal and RF integrated circuits.

The company was founded in 1984 by Dr. Ivan Pesic. The initial product, Utmost, quickly became the industry standard for parameter extraction, device characterization… Read More