Banner Electrical Verification The invisible bottleneck in IC design updated 1
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Managing Stress in 3D

Managing Stress in 3D
by Beth Martin on 09-02-2014 at 1:32 pm

A new publication on mechanical stress in integrated circuits, co-edited by Valeriy Sukharev, Principal Engineer for Calibre R&D at Mentor Graphics, has just been released by AIP Publishing. “Stress-Induced Phenomena and Reliability in 3D Microelectronics” includes 14 key papers from four international workshops … Read More


Design Collaboration across Multiple Sites

Design Collaboration across Multiple Sites
by Pawan Fangaria on 09-02-2014 at 12:00 pm

Any SoC or IC design project, whether implemented at the same design site or multiple sites requires some data management tools to manage things such as a central data repository, revision management of files, etc., for effective co-ordination of work among different team members. Given the challenge of meeting the shrinking… Read More


How to detect weak nodes in a power-off analog circuit?

How to detect weak nodes in a power-off analog circuit?
by Jean-Francois Debroux on 09-01-2014 at 4:00 pm

Most analog cells have a power off mode intended to reduce power consumption. In this mode, all the circuit branches between the supply lines are set in a high impedance mode by driving MOS gates to a blocking voltage. This is a somewhat similar situation to that in tri-state digital circuits.

When a branch is set in that high impedance… Read More


September is Semiconductor Design Webinar Month!

September is Semiconductor Design Webinar Month!
by Daniel Nenni on 09-01-2014 at 9:00 am

The nice thing about webinars is that if you register for the live one and you can’t attend you will still get first notice when the replay goes up. The other nice thing is that you can read a blog review of a webinar or whitepaper on SemiWiki first to see if it is worth your time. If you do attend a webinar you can also post a review of… Read More


Power and Thermal Analysis of Data Center and Server ICs

Power and Thermal Analysis of Data Center and Server ICs
by Daniel Payne on 08-31-2014 at 4:00 pm

The server market is a diverse, yet standardized market. The ICs and components designed and manufactured in final assemblies must meet form factor requirements for rack mount and blades. The form factor enclosures and the component placement dictate the thermal-mechanical properties and hence the thermal cooling limits … Read More


TCAD to SPICE Simulation of Power Devices

TCAD to SPICE Simulation of Power Devices
by Daniel Payne on 08-31-2014 at 1:30 pm

The periodic table shows that Silicon (Si) is in a column along with other elements like Carbon (C) and Germanium (Ge). With so much emphasis on Silicon, you’d think that the other semiconductor materials have been neglected a bit.

Silicon is a wonderful material and most of our consumer electronics and handheld devices … Read More


Webinar: Collaboration Within Dispersed Design Teams

Webinar: Collaboration Within Dispersed Design Teams
by Daniel Nenni on 08-30-2014 at 7:00 am

In the face of shrinking time-to-market windows, semiconductor companies are aggressively vying with each other to emerge with new or variants of existing ICs and SoCs to gain market share. The growth of the mobile market –wireless, networking, storage, and computing – as well as new areas such as the Internet of things (IoT) and… Read More


Assertion Synthesis: From Startup to Mainstream

Assertion Synthesis: From Startup to Mainstream
by Daniel Payne on 08-30-2014 at 7:00 am

In college many of us dreamed of starting up our own company by offering something new that has never been done before. Today I spoke by phone with Yunshan Zhuin Shanghai, and he has actually lived out this scenario by founding NextOp in 2006, then getting that company acquired by Atrentain 2012. The new capability that NextOp created… Read More


Transistor-level Sizing Optimization

Transistor-level Sizing Optimization
by Daniel Payne on 08-29-2014 at 4:00 pm

RTL designers know that their code gets transformed into gates and cells by using a logic synthesis tool, however these gates and cells are further comprised of transistors and sometimes you really need to optimize the transistor sizing to reach power, performance and area goals. I’ve done transistor-level IC design before,… Read More


FinFET Design for Power, Noise and Reliability

FinFET Design for Power, Noise and Reliability
by Daniel Payne on 08-29-2014 at 4:00 pm

IC designers have been running analysis tools for power, noise and reliability for many years now, so what is new when you start using FinFET transistors instead of planar transistors? Calvin Chow from ANSYS (Apache Design) presented on this topic earlier in the summer through a 33 minutewebinar that has been archived. There is… Read More