DAC starts in San Francisco on June 8th. The kickoff keynote at 9.20am that morning is by Brian Otis of Google. He is a director at Google[x]. According to Wikipedia:Google X, stylized as Google[x], is a semi-secret facility run by Google dedicated to making major technological advancements. It is located about a half mile from … Read More
Electronic Design Automation
ANSYS Event to Highlight Cutting Edge Technology Development
If you follow technology news, it would be hard to deny that we live in exciting times. In some ways there is an unparalleled amount of big and cool technology development going on right now. We all have followed the rise of Tesla Motors. They took over a long vacant US big-auto plant in Fremont and are reinventing the US automobile industry.… Read More
EDPS: Fins and FinFETs
Look at those dolphins with fins on their backs. Did you know that FinFETs are actually named after them since Chenming Hu and his team though that they looked like a fish’s fin? And since they invented FinFETs they got to name them too. But those dolphins also mean that it is nearly time for this years Electronic Design Process… Read More
What is Skipper?
What is Skipper? Well, it seems it’s a penguin in the movie Madagascar. And one of Barbie’s sisters. Who knew? But for Semiwiki readers it’s an integrated chip finishing platform from ICScape. Skipper can read in full-chip layout extremely fast, examine it and manipulate it in various ways, and write it out again.… Read More
Secret Sauce for Successful Mixed-signal SoCs
For a design engineer engulfed in the daily rigorous routine of having to keep in sync with updates from various design team members as well the dictums of the design management team, the task of remaining up-to-date with the design information is very often daunting.
What design changes have been checked in this week? Is the verification… Read More
Verifying the RTL Coming out of a High-Level Synthesis Tool
With High-Level Synthesis (HLS) the first benefit that comes to my mind is reduced design time, because coding with C or SystemC is more efficient than low-level RTL code. What I’ve just learned is that there’s another benefit, a reduction in the amount of functional simulation required. One HLS customer was able … Read More
The Earth is Not Flat; Neither is IP
Chip design is largely about assembling pre-designed IP, either developed in other groups in the same company, or brought in from a 3rd party, or occasionally developed within the SoC design group itself. But that makes it sound like it is a bunch of blocks linked together with some interconnect, but of course another important … Read More
CEVA Eyes DSP Scale in China’s $65 LTE Handsets
China Mobile’s bid to go for 3-mode Long-Term Evolution (LTE) has led to the first major breakthrough, $65 LTE handsets, and here baseband and application processors provided by chipmakers like Leadcore Technology, MediaTek and Spreadtrum Communications have all one thing in common: DSP cores from CEVA Inc.
The advent… Read More
Full-chip Multi-domain ESD Verification
ESD stands for electro-static discharge and deals with the fact that chips have to survive in an electrically hostile environment: people, testers, assembly equipment, shipping tubes. All of these can carry electric charge that has the “potential” (ho-ho) to damage the chip irreversibly. Historically this was… Read More
Medicals Marriage with Semis
I remember a couple of decades ago, my father used to go to a nearby doctor’s clinic to get his blood pressure and sugar levels checked. I guess, in around 1990s small electronic kits became available to measure these usual daily health indicators and instantly display the numbers. I bought a few for my father then. Today, the scene… Read More
Moving Beyond RTL at #62DAC