Synopsys IP Designs Edge AI 800x100
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EDA

Electronic Design Automation

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TSMC 10nm Readiness and 3DIC

TSMC 10nm Readiness and 3DIC
by Paul McLellan on 05-03-2015 at 1:00 am
Categories: EDA, FinFET, Foundries, IP, TSMC

At the TSMC Technology Symposium last month Suk Lee presented a lot of information on design enablement. Suk is an interesting guy with a unique background in ASIC, Semiconductor, EDA, and now Foundry. In baseball terms that would be like playing infield, outfield, home plate, and umpire!

Around the turn of the millennium Suk actually… Read More

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Fractal at DAC 2015 – What’s new?

Fractal at DAC 2015 – What’s new?
by Pawan Fangaria on 05-01-2015 at 1:00 pm
Categories: EDA, Fractal Technologies

I have been observing Fractal Technologiesexhibiting at DACyear after year, and every year they have demonstrated good value added features in their tools for SoC and IP development. This year at 52[SUP]nd[/SUP] DAC Fractal’s booth number is 1110. Earlier in this year Fractal had added a new ‘Cdiff’ feature in its flagship product… Read More

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Can You Really Automate Analog IC Layout?

Can You Really Automate Analog IC Layout?
by Daniel Payne on 04-30-2015 at 7:00 pm
Categories: EDA, Siemens EDA

Digital IC design has been largely automated with high-level languages, RTL coding, logic synthesis, and automated place and route tools. What about analog IC layout automation, is it possible? A few EDA companies think that it is possible and even practical. In recent memory there were two companies really focused on analog … Read More

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Automating Timing Closure Using Interconnect IP, Physical Information

Automating Timing Closure Using Interconnect IP, Physical Information
by Majeed Ahmad on 04-29-2015 at 1:00 pm
Categories: Arteris, EDA, IP

Timing closure is a “tortoise” for some system-on-chip (SoC) designers just the way many digital guys call RF design a “black art”. Chip designers often tell horror stories of doing up to 20 back-end physical synthesis place & route (SP&R) iterations with each iteration taking a week or more. “Timing closure”, a largely… Read More

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How Good Are Your Clocks?

How Good Are Your Clocks?
by Paul McLellan on 04-29-2015 at 7:00 am
Categories: EDA

One of the trickiest tasks in designing a modern SoC is getting the clock tree(s) right. The two big reasons for this:

  • the clocks can consume 30% or more of the power of the whole chip, so minimizing the number of buffers inserted is critical to keeping power under control
  • the clock insertion delay and clock skew have a major impact on
… Read More
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PDK Generation Needs Paradigm Shift

PDK Generation Needs Paradigm Shift
by Pawan Fangaria on 04-28-2015 at 4:00 pm
Categories: Coventor, EDA

For any semiconductor technology node to be adopted in actual semiconductor designs, the very first step is to have a Process Design Kit (PDK) developed for that particular technology node and qualified through several design tools used in the design flow. The development of PDK has not been easy; it’s a tedious, time consuming,… Read More

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SoC Debugging Just Got a Speed Boost

SoC Debugging Just Got a Speed Boost
by Daniel Payne on 04-28-2015 at 4:00 am
Categories: Cadence, EDA

Sure, design engineers can get more attention than verification engineers, but the greater number of verification engineers on SoC projects means that the verification task is a bigger bottleneck in a schedule than pure design work. A recent survey conducted at Cadence shows how verification effort can be divided into several,… Read More

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The 2015 DAC Designer and IP Track

The 2015 DAC Designer and IP Track
by Anne Cirkel on 04-27-2015 at 8:00 pm
Categories: EDA, Events, IP

What an exciting year for DAC with record submissions in nearly every category. Most impressive is the increase in Designer and IP Track submissions, content that is helping to continue to evolve and improve the show. If you haven’t already registered, why not do so now?

A brief bit of background about the conference: DAC’s roots… Read More

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Four Reasons Why Atmel is Ready to Ride the IoT Wave

Four Reasons Why Atmel is Ready to Ride the IoT Wave
by Majeed Ahmad on 04-27-2015 at 1:00 pm
Categories: EDA, IoT

In 2014, a Goldman Sachs’ report took many people by surprise when it picked Atmel Corp. as the company best positioned to take advantage of the rising Internet of Things (IoT) tsunami. At the same time, the report omitted tech industry giants like Apple and Google from the list of companies that could make a significant impact… Read More

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A Vision for FPGA Prototyping Realized

A Vision for FPGA Prototyping Realized
by Daniel Nenni on 04-27-2015 at 7:00 am
Categories: EDA, FPGA, S2C EDA

FPGA prototyping is beginning its move to the forefront of design and verification. More and more companies are turning to this technology not only for in-circuit testing and earlier software development but also for refining, validating, and implementing chip architecture. The increases in design size and complexity as well… Read More