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Secret Sauce for Successful Mixed-signal SoCs

Secret Sauce for Successful Mixed-signal SoCs
by admin on 03-31-2015 at 12:00 pm

For a design engineer engulfed in the daily rigorous routine of having to keep in sync with updates from various design team members as well the dictums of the design management team, the task of remaining up-to-date with the design information is very often daunting.

What design changes have been checked in this week? Is the verification… Read More


Verifying the RTL Coming out of a High-Level Synthesis Tool

Verifying the RTL Coming out of a High-Level Synthesis Tool
by Daniel Payne on 03-30-2015 at 9:30 pm

With High-Level Synthesis (HLS) the first benefit that comes to my mind is reduced design time, because coding with C or SystemC is more efficient than low-level RTL code. What I’ve just learned is that there’s another benefit, a reduction in the amount of functional simulation required. One HLS customer was able … Read More


The Earth is Not Flat; Neither is IP

The Earth is Not Flat; Neither is IP
by Paul McLellan on 03-29-2015 at 7:00 pm

Chip design is largely about assembling pre-designed IP, either developed in other groups in the same company, or brought in from a 3rd party, or occasionally developed within the SoC design group itself. But that makes it sound like it is a bunch of blocks linked together with some interconnect, but of course another important … Read More


CEVA Eyes DSP Scale in China’s $65 LTE Handsets

CEVA Eyes DSP Scale in China’s $65 LTE Handsets
by Majeed Ahmad on 03-27-2015 at 8:00 pm

China Mobile’s bid to go for 3-mode Long-Term Evolution (LTE) has led to the first major breakthrough, $65 LTE handsets, and here baseband and application processors provided by chipmakers like Leadcore Technology, MediaTek and Spreadtrum Communications have all one thing in common: DSP cores from CEVA Inc.

The advent… Read More


Full-chip Multi-domain ESD Verification

Full-chip Multi-domain ESD Verification
by Paul McLellan on 03-27-2015 at 7:00 am

ESD stands for electro-static discharge and deals with the fact that chips have to survive in an electrically hostile environment: people, testers, assembly equipment, shipping tubes. All of these can carry electric charge that has the “potential” (ho-ho) to damage the chip irreversibly. Historically this was… Read More


Medicals Marriage with Semis

Medicals Marriage with Semis
by Pawan Fangaria on 03-26-2015 at 7:00 pm

I remember a couple of decades ago, my father used to go to a nearby doctor’s clinic to get his blood pressure and sugar levels checked. I guess, in around 1990s small electronic kits became available to measure these usual daily health indicators and instantly display the numbers. I bought a few for my father then. Today, the scene… Read More


Verification IP for PCIe and AXI4

Verification IP for PCIe and AXI4
by Daniel Payne on 03-26-2015 at 2:00 pm

Engineers love acronyms and my latest blog post has three acronyms in the title alone, so hopefully you are doing or considering SoC designs with the AMBA AXI4(Advanced eXtensible Interface 4) interface specification along with PCI Express (Peripheral Component Interconnect Express). One big motivation for using semiconductor… Read More


25 Years of SNUG; 50 Years of Moore’s Law

25 Years of SNUG; 50 Years of Moore’s Law
by Paul McLellan on 03-26-2015 at 8:00 am

Earlier this week it was the Synopsys user group meeting SNUG. Not just any old SNUG but the 25th Annual SNUG. The first one was 15th March 1991 and was attended by 100 people. At the time, Synopsys had annual revenues of $22M. This year, the various SNUGs around the world will have a total attendance of 10,000 people and Synopsys revenue… Read More


Innovative MIPI Display Solution for UHD Mobile Devices

Innovative MIPI Display Solution for UHD Mobile Devices
by Pawan Fangaria on 03-25-2015 at 7:00 pm

Today an SoC cannot be without multiple IP blocks integrated together in the most optimal manner. In such an environment, it’s natural that interoperability and configurability of an IP get prime considerations to achieve the best PPA (Power, Performance and Area) for the SoC containing that IP. While PPA is a basic criterion … Read More


Chips and pins and layers within

Chips and pins and layers within
by Don Dingee on 03-25-2015 at 3:00 pm

After teams sweat the details of SoC and industrial design, they turn to printed circuit board designers for magic. Here are a pile of chips and passives, and a schematic for interconnecting them. This is how much physical space the board can occupy. Connectors have to be here, and here, and mounting holes there, and there. There … Read More