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WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4349
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4349
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

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SpyGlass World at Levi Stadium, October 21st

SpyGlass World at Levi Stadium, October 21st
by Bernard Murphy on 10-12-2015 at 2:00 pm
Categories: EDA, Synopsys

I suppose you might have something better to do next Wednesday but, seriously, it had better be pretty good. I admit I’m biased (I was the Atrenta CTO until very recently) but even given that and mixing metaphors, Atrenta really knocked it out of the park when they got the 49er stadium for their User Group meetings. You don’t have to … Read More

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Tensilica 4th generation DSP IP is a VPU

Tensilica 4th generation DSP IP is a VPU
by Eric Esteve on 10-12-2015 at 7:00 am
Categories: Cadence, IP

You may not know Tensilica DSP IP core, but you probably use Tensilica DSP powered systems in your day to day life. Every year, over 2 billion DSP cores equip IC in thousands of designs supporting IoT, Mobile Phones, Storage/SSD, Networking, Video, Security, Cameras… and more. Why DSP processing, the foundation of all Tensilica… Read More

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Meeting DFM Challenges with Hierarchical Fill Data Insertion

Meeting DFM Challenges with Hierarchical Fill Data Insertion
by Tom Dillinger on 10-11-2015 at 12:00 pm
Categories: EDA, Siemens EDA

To describe the latest methodology for the addition of Design for Manufacturability fill shapes to design layout data, it’s appropriate to borrow a song title from Bob Dylan – The Times They Are A Changin’. The new technical requirements are best summarized as: “The goal is now to add as much fill as possible, which (ideally) looks… Read More

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Applying EDA Concepts Outside Chip Design

Applying EDA Concepts Outside Chip Design
by Bernard Murphy on 10-11-2015 at 7:00 am
Categories: EDA

(I changed the title of this piece as an experiment) Paul McLellan recently wrote on the topic of new ventures crossing the chasm (getting from initial but bounded success to a proven scalable business). That got me to thinking about the EDA market in general. In some ways it has a similar problem, stuck at $5B or so and single-digit… Read More

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S2C ships UltraScale empowering SoFPGA

S2C ships UltraScale empowering SoFPGA
by Don Dingee on 10-10-2015 at 7:00 am
Categories: EDA, FPGA, S2C EDA

Most of the discussion around Xilinx UltraScale parts in FPGA-based prototyping modules has been on capacity, and that is certainly a key part of the story. Another use case is developing, one that may be even more important than simply packing a bigger design into a single part without partitioning. The real win with this technology… Read More

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Five Areas at #53DAC That Require Your Contribution

Five Areas at #53DAC That Require Your Contribution
by Daniel Payne on 10-09-2015 at 12:00 pm
Categories: EDA

The 53rd DAC (Design Automation Conference) is some 8 months away, however to make this conference and exhibit another success requires planning, people and awareness. That’s where you come in, because you can contribute your expertise in five different areas:

[LIST=1]

  • Panels – broad interest, interesting, timely,
    • … Read More
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    IMEC and Cadence Disclose 5nm Test Chip

    IMEC and Cadence Disclose 5nm Test Chip
    by Scotten Jones on 10-09-2015 at 7:00 am
    Categories: Cadence, EDA, ESD Alliance, Events

    Recently imec and Cadence disclosed that they had fabricated 5nm test chips. This afternoon Dan Nenni and I had a conference call with Praveen Raghavan, principal engineer at imec, and Vassilios Gerousis, distinguished engineer at Cadence to get more details on what the test chip is and what was learned.

    First off Vassilios really… Read More

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    Cadence Outlines Automotive Solutions at TSMC OIP Event

    Cadence Outlines Automotive Solutions at TSMC OIP Event
    by Tom Simon on 10-08-2015 at 12:00 pm
    Categories: Cadence, EDA, Events, TSMC

    I used to joke that my first car could survive a nuclear war. It was a 1971 Volvo sedan (142) that was EMP proof because it had absolutely no semiconductors in the ignition system, just points, condensers and a coil. If you go back to the Model T in 1915 you will see that the “on-board electronics” were not that different. However, today’s… Read More

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    Coventor prepping MEMS for CMOS integration

    Coventor prepping MEMS for CMOS integration
    by Don Dingee on 10-07-2015 at 12:00 pm
    Categories: Coventor, EDA

    About 11 months ago, I wrote a piece titled “Money for data and your MEMS for free.” In that, I took on the thinking that TSMC is just going to ride into town, fab trillions of IoT sensors, and they all will be 2.6 cents ten years from now. Good headline, but the technology and economics are not that simple. This may be the semiconductor … Read More

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    12 Reasons to Attend this Annual User Group Meeting for Transistor-level IC Designers

    12 Reasons to Attend this Annual User Group Meeting for Transistor-level IC Designers
    by Daniel Payne on 10-07-2015 at 7:00 am
    Categories: EDA, MunEDA

    My first job out of college was transistor-level circuit design of DRAMs at Intel, so I’ve continued to be fascinated with both the craft and science of designing, optimizing, verifying and debugging custom ICs. Last October I traveled to Munich, Germany to attend a two day user group meeting for engineers using tools from… Read More