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EDA

Electronic Design Automation

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High Level Synthesis. Are We There Yet?

High Level Synthesis. Are We There Yet?
by Paul McLellan on 06-16-2015 at 7:00 am
Categories: Cadence, STMicroelectronics, Synopsys, Xilinx

High level synthesis (HLS) seems to have been part of the backdrop of design automation for so long that it seems to be one of those things that nobody notices any more. But it has also crept up on people and gone from interesting technology to keep an eye on to getting genuine adoption. The first commercial product in the space was behavioral… Read More

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I Don’t Know Much About Aart…

I Don’t Know Much About Aart…
by Paul McLellan on 06-15-2015 at 7:00 am
Categories: EDA, Synopsys

Actually, like anyone who has been in EDA for more than a decade or two (or three) I know quite a bit about Aart. But I still learned quite a bit about his views at the Fireside Chat at DAC where Ed Sperling talked to Aart for three-quarters of an hour.

Aart has a great talent at taking various small trends in the industry and aggregating … Read More

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Design Data Management: An Analog IP Porting Case Study

Design Data Management: An Analog IP Porting Case Study
by Majeed Ahmad on 06-13-2015 at 9:00 am
Categories: Cliosoft, IP

IQ-Analog Corp. offers “off-the-shelf” data converter intellectual property (IP) for multiple foundries. The San Diego, California–based semiconductor design firm also provides analog front-end (AFE) technology that it tailors according to customer needs. And that’s where the dilemma begins.

IQ-Analog’s… Read More

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Why silicon photonics and 2.5D design go together

Why silicon photonics and 2.5D design go together
by Beth Martin on 06-10-2015 at 4:30 pm
Categories: EDA, Siemens EDA, Silicon Photonics

Silicon photonics is one of the upstart “More than Moore” technologies designed to enable the next generation of high-performance devices. Photonic design is the art of moving and transforming signals in the form of photons, allowing the message to literally travel at the speed of light, and bringing the promise of significant… Read More

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Predictions about EDA and IP at #52DAC

Predictions about EDA and IP at #52DAC
by Daniel Payne on 06-10-2015 at 4:00 am
Categories: EDA, General

On Sunday night at DAC this week I sat in the front row and listened to Gary Smith give his predictions about EDA and IP as an industry. His financial forecast was a $6.8B industry in 2015, growing to $9B in 2019. An ideal company for Wall Street to invest in would have slow and steady growth. If you add semiconductor IP into the forecast… Read More

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EDA Acquisition to Drive SoC realization

EDA Acquisition to Drive SoC realization
by Pawan Fangaria on 06-08-2015 at 8:00 pm
Categories: EDA, Synopsys

A week ago I was reading an article written by Daniel Nenni where he emphasised about semiconductor acquisitions to fuel innovation. We would see that in a larger space, not only in semiconductor and FPGA manufacturing companies (e.g. Intel and Altera) but also in the whole semiconductor ecosystem. If we see it from technical perspective,… Read More

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Next Generation Formal Technology to Boost Verification

Next Generation Formal Technology to Boost Verification
by Pawan Fangaria on 06-08-2015 at 12:00 pm
Categories: Cadence, EDA

With growing complexities and sizes of SoCs, verification has become a key challenge for design closure. There isn’t a single methodology that can provide complete verification closure for an SoC. Moreover creation of verification environment including hardware, software, testbench and testcases requires significant … Read More

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Synopsys to Acquire Atrenta

Synopsys to Acquire Atrenta
by Paul McLellan on 06-07-2015 at 11:17 pm
Categories: EDA, Synopsys

I was at the DAC kickoff this evening in the Intercontinental Hotel. I was talking to Dave DeMaria, the senior marketing guy at Synopsys and he told me of a couple of minor press releases due to hit the wire tomorrow morning, didn’t sound important enough to be blogworthy. Aart was there too although I didn’t speak to him.… Read More

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ESD Protection Network Checking is Difficult But Necessary

ESD Protection Network Checking is Difficult But Necessary
by Tom Simon on 06-06-2015 at 6:00 pm
Categories: EDA, Magwel

I’ve written before about anti-fuse non-volatile memory, where the gate oxide is intentionally damaged in order to create a readable bit of data, but this is what most circuit designers never want to have happen to their logic gates. However, since the advent of MOS transistors the issue of Electrostatic Discharge (ESD) and the… Read More

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Vacationing with the Fabless Semiconductor Ecosystem!

Vacationing with the Fabless Semiconductor Ecosystem!
by Daniel Nenni on 06-05-2015 at 4:00 pm
Categories: EDA, Events, IP, Synopsys

The Design Automation Conference is the largest and most diverse event in the fabless semiconductor ecosystem. Next week in San Francisco you will see technology and people you have never seen before. You will benefit from the efforts of hundreds of thousands of semiconductor professionals like myself who have dedicated their… Read More