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Magwel’s Current Tools Take an Active Role in Power Transistor Design

Magwel’s Current Tools Take an Active Role in Power Transistor Design
by Tom Simon on 12-03-2015 at 7:00 am

It often seems that semiconductor industry coverage focuses on large digital markets like microprocessors or high frequency analog designs for RF applications. Yes, these are large markets, but power transistors like IBGT and VFETS make up a large and crucial sector. Not only do they make their way into discretes, but they are… Read More


Academia and TCAD Grow Closer

Academia and TCAD Grow Closer
by Daniel Payne on 12-02-2015 at 12:00 pm

On my first trip to Austria for EDA business I traveled by car from Germany, and I couldn’t wait to see how fast we would travel on the fabled Autobahn. Oddly enough it was summertime and the Autobahn was filled with vacationing families driving cars with shiny, aluminum campers in tow, so our car only traveled about 60 mph, nothing… Read More


Advances in DDR IP Solution for High-Performance SoCs

Advances in DDR IP Solution for High-Performance SoCs
by Pawan Fangaria on 12-02-2015 at 7:00 am

In this era of high-performance, low-power, and low-cost devices coming up at an unprecedented scale, the SoCs can never attain the ultimate in performance; always there is scope for improvement. Several methods including innovative technology, multi-processor architecture, memory, data traffic management for low latency,… Read More


5 ways FPGA-based prototyping shrinks design time

5 ways FPGA-based prototyping shrinks design time
by Don Dingee on 12-01-2015 at 7:00 am

Engineers are trained to think linearly, along the lines of we started here, then we did this, and that, and this other stuff, and here is where we ended up. If you’ve ever presented in an internal review meeting, sales conference, or a TED-like event, you know that is a dangerous strategy in winning friends and influencing people.… Read More


An Easier Way to Reach Design Closure for SoC

An Easier Way to Reach Design Closure for SoC
by Daniel Payne on 11-30-2015 at 12:00 pm

It’s really challenging to reach design closure of an SoC by meeting timing constraints, staying within the power budget, tracking progress, communicating within the team, minimizing the floorplan, maximizing manufacturability and eliminating hotspots. Most SoC design teams have EDA tools from multiple vendors,… Read More


2016 EDA Dead Pool

2016 EDA Dead Pool
by Daniel Nenni on 11-30-2015 at 7:00 am

The most commonly asked question during conference calls with Wall Street of late is in regards to the massive consolidation the semiconductor industry is experiencing. How will the consolidation affect the Foundries? How will the consolidation affect EDA and IP? How will the consolidation affect the semiconductor industry… Read More


Coming to a Workstation Near You: Accellera’s Portable Stimulus Standard

Coming to a Workstation Near You: Accellera’s Portable Stimulus Standard
by Ellie Burns on 11-29-2015 at 7:00 am

Portable Stimulus has become such a popular standards topic of late that I thought it would be good to take a break this month from my low power series to bring you, my valued readers, more information about it from one of my colleagues, Dennis Brophy, who is working to help drive development of this standard within Accellera. I’ll Read More


How to Gain Low-Power at High-Performance

How to Gain Low-Power at High-Performance
by Pawan Fangaria on 11-28-2015 at 12:00 pm

In a world of smart devices, high performance is required in order to address several specific needs such as intelligent and immediate data processing for IoT applications, instant response from mobile devices, highly interactive user interfaces, and so on. Most of these devices are battery operated and hence require lower … Read More


Mentor takes IoT devices to cloud and back

Mentor takes IoT devices to cloud and back
by Don Dingee on 11-27-2015 at 12:00 pm

Walking into the Mentor Graphics booth at ARM TechCon, I was greeted by my friends Warren Kurisu and Shay Benchorin. It was good to see them both again. They were poised in front of a table with a Samsung tablet and a small Wi-Fi-ish box, next to a large Samsung printer. The demonstration was similar to a lobby check-in process, where… Read More


Power Reduction Verification Techniques Highlighted by Mentor at ARM Techcon

Power Reduction Verification Techniques Highlighted by Mentor at ARM Techcon
by Tom Simon on 11-24-2015 at 4:00 pm

Power management is a perennial topic these days, and it came up in several presentations at the recent ARM Techcon in Santa Clara in mid November. The techniques covered in these talks address dynamic and static power consumption. The IEEE 1801 standard deals with specifying power design intent in Universal Power Format (UPF)… Read More