As semiconductor professionals we all are familiar with Moore’s law. Respected Gordon Moore during year 1965-1975 observed and stated that, number of transistors in dense Integrated Circuit has doubled for approximately two years. In the present scenario, if we consider the complexity of Integrated Circuit and if we use the mathematical analysis with the fundamentals of Physics and relativity theory then for the shrinking process node, the law can be stated as ” Below 14 nm, the number of transistors in dense Integrated Circuit has to be doubled for approximately 32 months.” May be true till year 2019, the reasons are many, the exponential logic depth and computational efficiency, low power issues and need, on chip variation issues, latency, constraints at system level, parallelism, noise margins, crosstalk etc.
It is my observation and analysis in the past couple of years that at lower process nodes the real limitation is due to material properties, atomic spacing and the transfer of data due to the fabrication related issues. The technology shift can happen with the evolution of the process flow in the design of Integrated Circuits due to the issues related with the shrinking process node and the requirements of the analytical, mathematical and numerical modeling at the system, architecture and even at the design levels. .
At the engineering level the real bottleneck is the specification complexity, implementation and validation of the design at the system level. Even the practical limitation for the shrinking is the CAP theorem. According to CAP theorem, ” It is impossible for any computer system to simultaneously provide the consistency, partition tolerance and availability. “So there is limitation for the computing efficiency of the SOCs at the system architecture levels.
But the real limitation for shrinkage and computing performance is due to the space , energy, time issues. If we try to perceive the relativity theory of Einstein; then there is the limitation of the traveling particle with the speed of light. The carrier mobility due to the issues of the dielectric constants, conductivity of the material is the real limitation for the information transfer between the carriers. Another important limitation at the shrinking process node is the physical integration, synchronization to achieve the parallelism with high computational efficiency.
Another important limitations at device level are : aging, leakage, interfaces and contacts size and delay variations. So the real challenging phase for the semiconductor professionals is below 10nm process node.The real era of miniaturization can face challenges at 8 nm process node and there may be the evolution of design and process flow.
Probably during year 2019 one can expect the modified Moore’s law observation with the technological shift and changes in the design and manufacturing processes, where the number of transistors in dense integrated has to be doubled for approximately 36 to 38 months and may continue for almost one decade after 2019.
Although there are limitations, still we all are intelligent to design, innovate the complex SOCs. Let us hope for the great era of miniaturization!Share this post via: