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Cadence DSPs float for efficiency in complex apps

Cadence DSPs float for efficiency in complex apps
by Don Dingee on 09-29-2016 at 4:00 pm

Floating-point computation has been a staple of mainframe, minicomputer, supercomputer, workstation, and PC platforms for decades. Almost all modern microprocessor IP supports the IEEE 754 floating-point standard. Embedded design, for reasons of power and area and thereby cost, often eschews floating-point hardware… Read More


Power Exploration at RTL Design with Mentor PowerPro

Power Exploration at RTL Design with Mentor PowerPro
by Bernard Murphy on 09-29-2016 at 7:00 am

There was a comment recently that design for low power is not an event, it’s a process; that comment is absolutely correct. Power is affected by everything in the electronic ecosystem, from application software all the way down to layout and process choices. Yet power as a metric is much more challenging to model and control than … Read More


Synopsys Hosting Formal Methods in CAD Conference Next Week

Synopsys Hosting Formal Methods in CAD Conference Next Week
by Bernard Murphy on 09-27-2016 at 8:00 pm

SynopsysB

FMCAD (Formal Methods in Computer Aided Design) is a technical conference with a 20-year pedigree. This is a conference for serious formal methods teams. Key notes are from Berkeley and UCLA, committee members are all formal heavyweights and best I can tell, there is no exhibitors area.… Read More


Making photonic design more straightforward

Making photonic design more straightforward
by Don Dingee on 09-27-2016 at 4:00 pm

The arrival of optical computing has been predicted every year for the last fifteen years. As with any other technology backed by prolific research, lofty goals get dialed back as problems are identified. What emerges first is a set of use cases where the technology fits with practical, realizable implementations.

When it comes… Read More


Why is Low Frequency Noise Measurement for ICs Such a Big Deal?

Why is Low Frequency Noise Measurement for ICs Such a Big Deal?
by Daniel Payne on 09-27-2016 at 12:00 pm

Even digital designers need to be aware of how noise impacts their circuits because most clocked designs today use a Phase Locked Loop (PLL) block which contains a circuit called a Voltage Controlled Oscillator (VCO) that is quite sensitive in operation to the effects of noise and process variation. As process node scaling continues… Read More


Getting out of DIY Mode for Virtual Prototypes

Getting out of DIY Mode for Virtual Prototypes
by Don Dingee on 09-26-2016 at 4:00 pm

Virtual prototyping has, inexplicably, been largely a DIY thing so far. Tools and models have come from different sources with different approaches, and it has been up to the software development team to do the integration step and cobble together a toolchain and methodology that fits with their development effort.

That integration… Read More


Mentor Webinar on Power Exploration for Optimizing Power

Mentor Webinar on Power Exploration for Optimizing Power
by Bernard Murphy on 09-23-2016 at 8:00 pm

There are a lot of clever techniques to automatically find and even implement methods for register gating and memory gating, but the bulk of power-saving still depends on designer and architect insight based on expected range of use of a device, complemented by practical use-case simulations. Of course this team needs to be able… Read More


RTL Design Restructuring Explained

RTL Design Restructuring Explained
by Daniel Payne on 09-22-2016 at 4:00 pm

Modern SoC designs can use billions of transistors where transistors are grouped into gates, then gates grouped into cells, then cells grouped into blocks, blocks grouped into modules, and so on, creating a complex hierarchy. What a front-end designer conceives of logically for a hierarchy will differ from how an optimized physical… Read More


Solutions for Variation Analysis at 16nm and Beyond

Solutions for Variation Analysis at 16nm and Beyond
by Tom Simon on 09-22-2016 at 7:00 am

Variation is still the tough nut to crack for advanced process nodes. The familiar refrain of lower operating voltages and higher performance requirements make process variation an extremely important design consideration. As far back as the early 2000’s design teams have been looking for a better approach to model variation… Read More


3 Small-Team Design Productivity Challenges Managed

3 Small-Team Design Productivity Challenges Managed
by Don Dingee on 09-21-2016 at 4:00 pm

“Data management tools? We use small teams doing small designs. Each project only has two or three designers. Everyone uses the same EDA tools. Why do we need another tool for collaboration?” Good question. If you enjoy frequent meetings and redoing work because someone didn’t understand the status of IP blocks, the answers may… Read More