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Electronic Design Automation
There are a lot of clever techniques to automatically find and even implement methods for register gating and memory gating, but the bulk of power-saving still depends on designer and architect insight based on expected range of use of a device, complemented by practical use-case simulations. Of course this team needs to be able… Read More
Modern SoC designs can use billions of transistors where transistors are grouped into gates, then gates grouped into cells, then cells grouped into blocks, blocks grouped into modules, and so on, creating a complex hierarchy. What a front-end designer conceives of logically for a hierarchy will differ from how an optimized physical… Read More
Variation is still the tough nut to crack for advanced process nodes. The familiar refrain of lower operating voltages and higher performance requirements make process variation an extremely important design consideration. As far back as the early 2000’s design teams have been looking for a better approach to model variation… Read More
“Data management tools? We use small teams doing small designs. Each project only has two or three designers. Everyone uses the same EDA tools. Why do we need another tool for collaboration?” Good question. If you enjoy frequent meetings and redoing work because someone didn’t understand the status of IP blocks, the answers may… Read More
Most of what you have read about design for low power has probably focused on mobile devices where power consumption constraints tend to outweigh performance objectives. These devices use aggressive power switching strategies, based on the reasonable assumption that parts or all of the device can be powered down at any given … Read More
It is a busy month for book signings but it is a pleasure to do it for the greater good of the semiconductor industry. It really is an honor to meet the people who keep our electronic devices on the leading edge of technology, absolutely.
The Linley Processor Conference is on September 27[SUP]th[/SUP]and 28[SUP]th[/SUP] at the Hyatt… Read More
Many tools find clock domain crossings (CDCs) in FPGA designs. Some don’t find the right ones since they don’t comprehend things like in-house synchronizer constructs. Some find too many based on misunderstanding intent, inaccurate constraints, and other factors that lead to noise.… Read More
As most of you know SemiWiki published a book which is a really nice history of the fabless semiconductor ecosystem. Thousands of people have copies, we have received many compliments on it, and we are very proud. As a thank you to all SemiWiki members I would like to offer a free electronic version of the book (PDF). You can access it… Read More
One of the great advantages of emulation is that runtimes are much faster than for simulation – sufficiently fast that you can really debug hardware together with software for comprehensive use-case testing. A not so great aspect is that emulators are expensive and, until relatively recently, not particularly easy to share across… Read More
Today, in the context of functional verification, industry trends are based on the needs of prominent vertical markets. There is some overlap in what these markets need, but there are some use models that are very specific to each market.
We assert this because we have a lot of customers asking about emulation solutions not from … Read More
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AI RTL Generation versus AI RTL Verification