The world-renowned statistician, Professor George Box, said, “Essentially, all models are wrong, but some are useful.” — that quote was the theme for one of the technical talks at the recent MOS-AK Workshop, held at UC-Berkeley.
The workshop provided presentations from the leading developers of compact device models. The audience spanned the full range of the semiconductor industry, including representatives from foundries, model characterization services firms, academic researchers investigating emerging device technologies, and design companies. The amount and breadth of technical information discussed was vast — here are but a few highlights.
Peter Lee, Micron Memory Japan
Peter is the Chairman of the Compact Model Coalition. He provided an overview of the scope and responsibilities of the CMC, an organization that evaluates and qualified fundamental model formats.
Models are continually evolving, as the CMC strives to improve accuracy and simulation performance to meet the needs of the semiconductor industry. The CMC is also focused on promoting model portability and support across a range of commercial and open source simulation tools. To that effect, models are being developed and qualified in the Verilog-A semantics. (More on Verilog-A modeling shortly.)
The scope of the CMC has expanded over the years. The group has released a standard application programming interface definition, currently for C-based model code. This Open Modeling Interface API (OMI) enables the foundry to implement proprietary formulations for complex effects that impact the base device parameter model values — e.g., layout-dependent effects, self-heating temperature distribution, aging reliability factors. Standardizing the API would enable plugging in these formulations to all circuit simulators supporting the standard without modifications.
Industry participation in the CMC is broad, ensuring that the testing and qualification of proposed model revisions is exercised across many, varied circuit applications. The CMC priorities for model development (and funding) are driven by the members. Peter provided the following development list of recent projects, from the various CMC working groups (http://projects.si2.org/CMC_index.php):
- FD-SOI models to 10nm: BSIM-IMG, HiSIM-SOTB newly standardized
- Reverse recovery diode behavior (DDIOE-CMC model)
- Gallium Nitride (GaN) high electron mobility transistor (HEMT) model standardization
The topic of the Lunch Panel Discussion was the compatibility of the current CMC compact model License with other Open Source licenses (particularly the Gnu Public License). The Xyce circuit simulator team determined the CMC and GPL licenses did not inherently conflict. However, aspects of the CMC license kept Open Source codes (such as Qucs) from being included in the main Linux distributions. Peter noted that Si2 is in the process of moving to the Apache 2.0 license for all their Open Source projects. Major efforts to make this move will be done in 2017. Members of the panel discussion expressed that this should eliminate the difficulties seen by the GPL-licensed codes.
If your firm is not currently a member of the CMC, please consider the value of participating in guiding the priorities and qualification testing of advanced model releases.
Tianshi Wang, UC-Berkeley
The modeling team at UC-B presented an update on their recent work. One key area is to define a standard format for table-based (non-physical) models. These model simplifications offer a significant evaluation speedup for transient (and DC) simulations, utilizing multi-dimensional interpolation algorithms.
Other model research areas that Tianshi presented included memristor devices, and a detailed snapback model for ESD structures.
Larry Dunleavy, Modelithics, Inc.
Modelithics provides modeling services and releases models for commercial off-the-shelf (COTS) part numbers. Larry also indicated that Verilog-A is emerging as the preferred semantics for portability across simulators, a key requirement for the thousands of COTS models that Modelithics supports. And, as Peter indicated in his talk, Larry also highlighted the emergence of GaN device modeling as a key focus for COTS power amplifiers — accurate impedance models are needed to design for optimal power transfer.
Larry did provide a cautionary comment, however — the breadth of Verilog-A semantics supported by various simulators differs, as not all math functions are supported by all products. The CMC is addressing this issue — a working group has been established to prepare recommendations for Verilog-A coding styles.
Josef Watts, GLOBALFOUNDRIES
One of the areas where current FinFET device modeling is perhaps the weakest is incorporating the effects of parasitic gate resistance. The current BSIM-CMG algorithms carries forward the approach used for planar devices, namely that an additional parasitic resistance is added to the external gate resistance, equal to 1/3rd of the device Rg:
In the presentation from GLOBALFOUNDRIES, the limitations of this approach for FinFET devices were discussed — the gate resistance combined with the additional gate-to-drain/source/substrate parasitic capacitances as the gate traverses between fins requires a more detailed model.
“This is mandatory for accurate small-signal simulation.”,Josef highlighted. “We have developed a more sophisticated FinFET device model, and corresponding parasitic extraction calculations.”
Although this method is currently proprietary to GLOBALFOUNDRIES, I observed the CMC members at the workshop taking detailed notes.
These were but a few of the technical highlights and achievements discussed at the workshop.
The MOS-AK workshop organizer, Wladek Grabinski, wrapped up the meeting with an outlook for upcoming modeling workshops, and a review of the books and technical materials available at the MOS-AK web site: www.mos-ak.org
The MOS-AK Modeling Working Group has various deliverables and initiatives, including: a book entitled “Open Source CAD Tools for Compact Modeling” <www.mos-ak.org/books>; an open Verilog-A directory with models <http://www.mos-ak.org/open_dir/>; and, supporting FOSS TCAD/CAD software.
The MOS-AK Association plans to continue its standardization efforts by organizing additional compact modeling meetings, workshops and courses in Europe, USA, India and China throughout 2017 year, including:
- Spring MOS-AK Workshop in Lausanne at DATE Conference (March 31 2017) http://www.mos-ak.org/lausanne_2017
- 2nd Sino MOS-AK Workshop in Hangzhou (June 2017) http://www.mos-ak.org/hangzhou_2017
- 15th MOS-AK ESSDERC/ESSCIRC Workshop in Leuven (Sept.11, 2017) http://www.mos-ak.org/leuven_2017
If you are involved in developing or supporting device models for circuit designers, I would encourage you to become an active participant in the MOS-AK community.
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