I’ll never forget first learning about Xilinx when they got started back in 1984, because the concept of a Field Programmable Gate Array (FPGA) was so simple and elegant, it was rows and columns of logic gates that a designer could program to perform any logic function, then connect that logic to IO pads to drive other chips … Read More
Electronic Design Automation
Netlist CDC. Why You Need it and How You do it.
The most obvious question here is “why do I need netlist CDC?” A lot of what you’re looking for in CDC analysis is really complex behaviors, like handshakes between different clock domains, correct gray coding in synchronizing FIFOs, eliminating quasi-static signals and the like. Deeply functional, system-level intent stuff.… Read More
High-throughput Workloads Get a Boost from Altair
Altair PBS Professional™ is the trusted leader in high-performance computing workload management. It efficiently schedules HPC workloads across all forms of computing infrastructure, and it scales easily to support systems of any size — from clusters to the largest supercomputers.
Scheduling for high-throughput workloads… Read More
HCL Webinar Series – HCL Compass Delivers Defect Tracking and More
Similar to my last post on the HCL DevOps webinar series, I will cover their presentation of HCL Compass in a webinar that was recorded on July 29 about how HCL Compass delivers defect tracking and more.
This webinar was presented by Steve Boone, head of product management at HCL Software DevOps, Howie Bernstein, product manager… Read More
ARC Processor Virtual Summit!
The ARC Processor has a rich history. Originally named the Argonaut RISC Processor, it was designed for the Nintendo Game Systems in the 1990s. Argonaut Technologies Limited later became ARC International. My first intimate exposure to ARC was in 2009 when Virage Logic acquired ARC. A year later Virage was acquired by Synopsys… Read More
White Paper – Mixed Signal Verification for Nanometer SOCs
The number of touchpoints between analog and digital circuits in high performance SoCs is increasing. This is not a problem because it is possible to implement critical analog blocks directly on nanometer scale digital ICs. However, in many cases digital interfaces or digital feedback circuitry configures these analog blocks… Read More
CEO Interview: Anna Fontanelli of Monozukuri
Anna has more than 25 years of expertise in managing complex R&D organizations and programs, giving birth to a number of innovative EDA technologies. She has pioneered the study and development of several generations of IC and package co-design environments and has held senior positions at leading semiconductor and EDA … Read More
The Big Three Weigh in on Emulation Best Practices
As software content increases in system-on-chip and system-in-package designs, emulation has become a critical enabling technology for the software team. This technology offers software developers the opportunity to verify their code in against a high-fidelity model of the target system that actually executes fast enough… Read More
CEO Interview: Isabelle Geday of Magillem
Isabelle Geday is the Founder and CEO of Magillem Design Services, headquartered in Paris, France. Isabelle has over 40 years of experience creating innovative platform solutions, in various industries such as oil, telecommunications, IT and EDA. She has a proven track record in managing startup companies internationally,… Read More
Cadence Increases Verification Efficiency up to 5X with Xcelium ML
SoC verification has always been an interesting topic for me. Having worked at companies like Zycad that offered hardware accelerators for logic and fault simulation, the concept of reducing the time needed to verify a complex SoC has occupied a lot of my thoughts. The bar we always tried to clear was actually simple to articulate… Read More


AI Bubble?