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Why In-Memory Computing Will Disrupt Your AI SoC Development

Why In-Memory Computing Will Disrupt Your AI SoC Development
by Ron Lowman on 03-22-2021 at 6:00 am

dwtb q121 in memory comp fig1.jpg.imgw .850.x 1

Artificial intelligence (AI) algorithms thirsting for higher performance per watt have driven the development of specific hardware design techniques, including in-memory computing, for system-on-chip (SoC) designs. In-memory computing has predominantly been publicly seen in semiconductor startups looking to disrupt… Read More


RIP Jim Hogan – An Industry Icon

RIP Jim Hogan – An Industry Icon
by Bernard Murphy on 03-21-2021 at 8:00 am

RIP Jim Hogan

An unavoidable consequence of getting older is that more frequently our friends and colleagues unexpectedly leave us for their final venture. Jim Hogan, widely known and loved in the semiconductor industry, has passed on. He will leave a substantial hole in the hearts of many. Always ready with seasoned advice, a sympathetic … Read More


Electromagnetic and Circuit RLCK Extraction and Simulation for Advanced Silicon, Interposers and Package Designs

Electromagnetic and Circuit RLCK Extraction and Simulation for Advanced Silicon, Interposers and Package Designs
by Tom Dillinger on 03-16-2021 at 6:00 am

spiral complex

For years, there have been rather distinct domains for the extraction of interconnect models from physical design data.

Chip designers commonly focused on RC parasitics for circuit/path delay calculations and dynamic I*R voltage drop analysis.  The annotation of extracted parasitics to a netlist model required the layout… Read More


CEO Interview: R.K. Patil of Vayavya Labs

CEO Interview: R.K. Patil of Vayavya Labs
by Daniel Nenni on 03-12-2021 at 6:00 am

RK Patil 1

RK has over 25 years of industry experience in the domain of Telecom, Embedded software and Semiconductors. Before co-founding Vayavya, he was a co-founder at Smart Yantra Technologies, where he has held various positions in engineering, marketing and management. At Vayavya RK is responsible for overall management and strategic… Read More


VersionVault brings SCM/DM capabilities to EDA World – with Cadence Virtuoso Integration

VersionVault brings SCM/DM capabilities to EDA World – with Cadence Virtuoso Integration
by manish_virmani on 03-11-2021 at 10:00 am

VersionVault Cadence Integration

HCL VersionVault is a secure enterprise solution for version control and configuration management. With HCL VersionVault – Cadence Virtuoso Integration, VersionVault brings its enterprise configuration management capabilities to analog and mixed signal designers. This integration enables designers to take advantage… Read More


Using IP Interfaces to Reduce HPC Latency and Accelerate the Cloud

Using IP Interfaces to Reduce HPC Latency and Accelerate the Cloud
by Scott Durrant Gary Ruggles on 03-11-2021 at 6:00 am

dwtb q121 in memory comp fig1.jpg.imgw .850.x

IDC has forecasted that over the next five years, the Global Datasphere — the amount of data that’s created, transferred over the network and stored each year — will increase by over 3X to 175 zettabytes (Figure 1). Much of this is driven by the Internet of Things (IoT), video applications (including video streaming,… Read More


Cadence Underlines Verification Throughput at DVCon

Cadence Underlines Verification Throughput at DVCon
by Bernard Murphy on 03-10-2021 at 6:00 am

Verification Throughput min

Paul Cunningham, CVP and GM of the System Verification Group at Cadence gave the afternoon Keynote on Tuesday at DVCon and doubled down on his verification-throughput message. At the end of the day, what matters most to us in verification is the number of bugs found and fixed per dollar per day. You can’t really argue with that message.… Read More


USB 3.2 Helps Deliver on Type-C Connector Performance Potential

USB 3.2 Helps Deliver on Type-C Connector Performance Potential
by Tom Simon on 03-08-2021 at 10:00 am

USB 3.2 Lane Usage

Despite sounding like a minor enhancement version for USB, USB 3.2 introduces many important changes for the USB specification. To see where USB has come from and where it is going, it is essential to look at what is found in USB 3.2. The other salient point is that now the Type-C connector has split out from the underlying USB specification… Read More


Features of Short-Reach Interface IP Design

Features of Short-Reach Interface IP Design
by Tom Dillinger on 03-08-2021 at 6:00 am

eye diagram

The emergence of advanced packaging technologies has led to the introduction of new types of data communication interfaces.  There are a number of topologies that are defined by the IEEE 802.3 standard, as well as the Optical Internetworking Common Electrical I/O CEI standard. [1,2]  (Many of the configurations of interest … Read More


Perforce Embedded DevOps Summit 2021 and the Path to Secure Collaboration on the Cloud

Perforce Embedded DevOps Summit 2021 and the Path to Secure Collaboration on the Cloud
by Mike Gianfagna on 03-04-2021 at 10:00 am

Perforce Embedded DevOps Summit 2021 and the Path to Secure Collaboration on the Cloud

Perforce recently held their virtual Embedded DevOps Summit. There was a lot of great presentations across many disciplines. Of particular interest to me, and likely to the SemiWiki readership as well, was a presentation by Warren Savage entitled Secure Collaboration on a Cloud-based Chip Design Environment. I’ll provide … Read More