Banner Electrical Verification The invisible bottleneck in IC design updated 1
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An Invited Talk at IEDM: Intel’s Mr. Transistor Presents The Incredible Shrinking Transistor – Shattering Perceived Barriers and Forging Ahead

An Invited Talk at IEDM: Intel’s Mr. Transistor Presents The Incredible Shrinking Transistor – Shattering Perceived Barriers and Forging Ahead
by Mike Gianfagna on 12-16-2024 at 10:00 am

An Invited Talk at IDEM Intel’s Mr. Transistor Presents The Incredible Shrinking Transistor – Shattering Perceived Barriers and Forging Ahead

IEDM turned 70 last week. This was cause for much celebration in the form of special events. One such event was a special invited paper on Tuesday afternoon from Intel’s Tahir Ghani, or Mr. Transistor as he is known. Tahir has been driving innovation at Intel for a very long time. He is an eyewitness to the incredible impact of the Moore’s… Read More


IEDM Opens with a Big Picture Keynote from TSMC’s Yuh-Jier Mii

IEDM Opens with a Big Picture Keynote from TSMC’s Yuh-Jier Mii
by Mike Gianfagna on 12-12-2024 at 10:00 am

IEDM Opens with a Big Picture Keynote from TSMC’s Yuh Jier Mii

The main program for the 70th IEDM opened on Monday morning in San Francisco with an excellent keynote from Dr. Yuh-Jier Mii, Executive Vice President and Co-Chief Operating Officer at TSMC. Dr. Mii joined TSMC in 1994. Since then, he has contributed to the development and manufacturing of advanced CMOS technologies in both fab

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Accellera 2024 End of Year Update

Accellera 2024 End of Year Update
by Bernard Murphy on 12-11-2024 at 6:00 am

logo accellera min

From my viewpoint, standards organizations in semiconductor design always looked like they were “sharpening the saw”: further polishing/refining what we already have but not often pushing on frontiers. Very necessary of course to stabilize and get common agreement in standards but equally always seeming to be behind the innovation… Read More


CEO Interview: GP Singh from Ambient Scientific

CEO Interview: GP Singh from Ambient Scientific
by Daniel Nenni on 12-06-2024 at 6:00 am

GP Sir Photo

Gajendra Prasad Singh, also known as GP Singh, is a seasoned tech professional with over 26 years of experience in advanced semiconductor chips. With a zeal to solve the most complex technical problems, he harped on a difficult journey to create programmable AI Microprocessors, that provide high-performance in a cost-effective… Read More


PDF Solutions Hosts Executive Conference December 12 on AI’s Power to Transform Semiconductor Design and Manufacturing

PDF Solutions Hosts Executive Conference December 12 on AI’s Power to Transform Semiconductor Design and Manufacturing
by Daniel Nenni on 12-05-2024 at 6:00 am

PDF Solutions LI Post on Conference

PDF Solutions, Inc. will host an AI Executive Conference Thursday, December 12, in San Francisco featuring keynotes, presentations, panels and demonstrations offering insights into the power of AI to transform semiconductor design and manufacturing. The conference immediately follows the 70th Annual IEEE International… Read More


Is AI Intelligent? Insights from Ronjon Nag’s Presentation

Is AI Intelligent? Insights from Ronjon Nag’s Presentation
by Admin on 12-01-2024 at 8:00 am

Is AI Intellegint SemiWiki

In his keynote at the 2024 31st IEEE Electronic Design Process Symposium, Dr. Ronjon Nag, an adjunct professor at Stanford Medicine and president of the R42 Group, poses the provocative question: “Is AI Intelligent?” Drawing from four decades of pioneering work in AI, Nag blends personal anecdotes, scientific … Read More


CEO Interview: Rajesh Vashist of SiTime

CEO Interview: Rajesh Vashist of SiTime
by Daniel Nenni on 11-28-2024 at 10:00 am

Fotosbyt/san jose

Rajesh Vashist is SiTime’s Chairman and Chief Executive Officer and has served in this role since September 2007. Prior to joining SiTime, Mr. Vashist served as CEO and chairman of the board of directors of Ikanos Communications, Inc., a semiconductor and software development company, from July 1999 to October 2006. Mr. Vashist… Read More


Compiler Tuning for Simulator Speedup. Innovation in Verification

Compiler Tuning for Simulator Speedup. Innovation in Verification
by Bernard Murphy on 11-27-2024 at 6:00 am

Innovation New

Modern simulators map logic designs into software to compile for native execution on target hardware. Can this compile step be further optimized? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas.… Read More


Scaling AI Data Centers: The Role of Chiplets and Connectivity

Scaling AI Data Centers: The Role of Chiplets and Connectivity
by Kalar Rajendiran on 11-26-2024 at 6:00 am

Building the Modern Data Centre AI Compute Nodes

Artificial intelligence (AI) has revolutionized data center infrastructure, requiring a reimagining of computational, memory, and connectivity technologies. Meeting the increasing demand for high performance and efficiency in AI workloads has led to the emergence of innovative solutions, including chiplets, advanced… Read More


Cadence Paints a Broad Canvas in Automotive

Cadence Paints a Broad Canvas in Automotive
by Bernard Murphy on 11-25-2024 at 6:00 am

automotive trends min

Cadence recently launched a webinar series on trends and challenges in automotive design. They contribute through IP from their Silicon Solutions Group, a comprehensive spectrum of design tooling and through collaborative development within a wide partner ecosystem. This collaboration aims to support and advance progress… Read More