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DAC 800x100
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SoC Power Integrity Challenges

SoC Power Integrity Challenges
by Daniel Payne on 04-08-2013 at 4:46 pm

At DAC in 2012 I visited a few dozen EDA companies and blogged 32 articles, however I didn’t get to see what Apache Design (now a subsidiary of ANSYS) had to say. I did have 20 minutes today to watch their latest video on SoC Power Integrity Challenges and decided to share what I learned. If you want to watch the video at Tech Online,… Read More


Watch the Clock

Watch the Clock
by Paul McLellan on 03-05-2013 at 2:24 pm

Clock gating is one of the most basic weapons in the armoury for reducing dynamic power on a design. All modern synthesis tools can insert clock gating cells to shut down clocking to registers when the contents of the register are not changing. The archetypal case is a register which sometimes loads a new value (when an enable signal… Read More


Another Winner at DesignCon

Another Winner at DesignCon
by Daniel Payne on 02-08-2013 at 5:44 pm

After a show like DesignConwraps up we get a chance to ask ourself what it all meant, and how was this year different than last year. Reading through many posts about DesignCon I came to discover that the Awards at DesignCon are less contentious than at CES, and also that ANSYSreceived a DesignVision awardfor the 2nd year running. … Read More


A Brief History of Apache Design

A Brief History of Apache Design
by Daniel Nenni on 01-16-2013 at 3:00 pm

Apache Design Solutions was founded in 2001 by Andrew Yang and three researchers from HP Labs (Norman Chang, Shen Lin, Weize Xie). They realized that engineers striving to meet the goal of increased device miniaturization, as defined by Moore’s Law, would eventually hit stumbling blocks in their progress. The founding team believed… Read More


ESD Check Methodology

ESD Check Methodology
by Paul McLellan on 01-11-2013 at 5:12 pm

In Pune at the start of the month, Norman Chang, Ting-Sheng Ku, Jai Pollayil of Apache/Ansys and NVIDIA presented and ESD check methodologywith Fast Full-chip Static and Macro-level Dynamic Solutions . ESD stands for Elecro-Static Discharge and is basically injecting very high static voltages (think how your hand gets charged… Read More


Apache/Ansys presents: 3DIC thermal, transmission lines, low frequency analysis

Apache/Ansys presents: 3DIC thermal, transmission lines, low frequency analysis
by Paul McLellan on 12-16-2012 at 10:00 pm

Late in January it is DesignCon at the Santa Clara convention center from January 28th-31st. Details are here.

On Tuesday from 11.05 to 11.45 Apache and Ansys will be presenting on Thermal Co-analysis of 3D IC/packages/system. This is being presented by a whole team of people: Stephen Pan, senior product specialist at ANSYS; Norman… Read More


Apache Presents: ESD analysis

Apache Presents: ESD analysis
by Paul McLellan on 12-13-2012 at 1:15 am

The 26th Conference on VLSI Design will be in Pune, India from January 5th to 10th at the Hyatt Regency. Details on the conference here. Registration here. I happened to be involved in the first of these conferences, which was held in Edinburgh where I was wrapping up my PhD. It was in the considerably less palatial surroundings of … Read More


Apache Power Artist Capabilities II

Apache Power Artist Capabilities II
by Paul McLellan on 12-09-2012 at 4:00 pm

This is the second part of my discussion with Paul Traynar, Apache’s PowerArtist guru. The first part discussed sequential reduction capabilities. Part I was here.

There are two big challenges with doing power analysis at the RTL level. Firstly, how do you get an accurate enough model of what the design will dissipate given… Read More


Apache Power Artist Capabilities I

Apache Power Artist Capabilities I
by Paul McLellan on 12-06-2012 at 2:05 pm

I sat down last week with Paul Traynar who was over from UK. He is Apache’s PowerArtist guru. The first thing we talked about was PowerArtist’s sequential power reduction capabilities.

Forward propagation of enables means that when a register is clock gated and feeds a downstream register then that register can be… Read More