This is another installment covering TSMC’s very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC’s vast ecosystem collaborates with each other and with TSMC. The talk covered here focuses on a complete on-die clock … Read More
Author: Mike Gianfagna
Dolphin Design – Delivering High-Performance Audio Processing with TSMC’s 22ULL Process
TSMC held their very popular Open Innovation Platform event (OIP) on August 25. The event was virtual of course and was packed with great presentations from TSMC’s vast ecosystem. One very interesting and relevant presentation was from Dolphin Design, discussing the delivery of high-performance audio processing using TSMC’s… Read More
Alchip at TSMC OIP – Reticle Size Design and Chiplet Capabilities
This is another installment covering TSMC’s very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC’s vast ecosystem collaborates with each other and with TSMC. This presentation is from Alchip, presented by James Huang,… Read More
Cerebras and Analog Bits at TSMC OIP – Collaboration on the Largest and Most Powerful AI Chip in the World
This is another installment covering TSMC’s very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC’s vast ecosystem collaborates with each other and with TSMC. The topic at hand was full of superlatives, which isn’t surprising… Read More
Webinar: Maximize Performance Using FPGAs with PCIe Gen5 Interfaces
FPGAs are a popular method to implement hardware accelerators for applications such as AI/ML, SmartNICs and storage acceleration. PCIe Gen5 is a high bandwidth communication protocol that is a key enabler for this class of applications. Putting all this together presents significant demands on the FPGA for performance and … Read More
Moving to Deeply Scaled Nodes for Power? There is a Better Way
Did you know you can save 30% to 60% power without spending a fortune on a process migration? There is a better way than moving to deeply scaled nodes for power. Read on…
Have you heard of AGGIOS? You will. The name stands for AGGregated IO Systems, and a team of ex ARM and Qualcomm engineers are re-inventing power management. I’ll explain… Read More
HCL Webinar Series – HCL Compass Delivers Defect Tracking and More
Similar to my last post on the HCL DevOps webinar series, I will cover their presentation of HCL Compass in a webinar that was recorded on July 29 about how HCL Compass delivers defect tracking and more.
This webinar was presented by Steve Boone, head of product management at HCL Software DevOps, Howie Bernstein, product manager… Read More
The Big Three Weigh in on Emulation Best Practices
As software content increases in system-on-chip and system-in-package designs, emulation has become a critical enabling technology for the software team. This technology offers software developers the opportunity to verify their code in against a high-fidelity model of the target system that actually executes fast enough… Read More
NetApp: Comprehensive Support for Moving Your EDA Flow to the Cloud
With this post, we welcome NetApp to the SemiWiki family. NetApp was founded in 1992 with a focus on data storage solutions. Initial market segments were high-performance computing (HPC) and EDA and their first customers were EDA and semiconductor companies. NetApp has become a primary force in on-premise data management for… Read More
Cadence Increases Verification Efficiency up to 5X with Xcelium ML
SoC verification has always been an interesting topic for me. Having worked at companies like Zycad that offered hardware accelerators for logic and fault simulation, the concept of reducing the time needed to verify a complex SoC has occupied a lot of my thoughts. The bar we always tried to clear was actually simple to articulate… Read More
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