Security in I/O Interconnects

Security in I/O Interconnects
by Mike Gianfagna on 03-25-2020 at 10:00 am

shutterstock 1221815029

I got a chance to chat with Richard Solomon at Synopsys recently about a very real threat for all of us and what Synopsys is doing about it. No, the topic isn’t the Coronavirus, it’s one that has been around a lot longer and will continue to be a very real threat – data and interconnect security.

First, a bit about Richard. He is the technical… Read More


Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion

Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion
by Mike Gianfagna on 03-24-2020 at 10:00 am

Screen Shot 2020 03 14 at 5.36.37 PM

I had the opportunity to preview an upcoming SemiWiki webinar on IR drop and power integrity. These topics, all by themselves, have real stopping power. Almost everyone I speak with has a story to tell about these issues in a recent chip design project. When you combine hot topics like this with a presentation that details the collaboration… Read More


Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput

Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput
by Mike Gianfagna on 03-23-2020 at 6:00 am

FINAL2 Digital FF iSpatial Flow hi res

Artificial intelligence (AI) and machine learning (ML) are hot topics. Beyond the impact these technologies are having on the world around us, they are also having impact on the semiconductor and EDA ecosystem. I posted a blog last week that discussed how Cadence views AI/ML, both from a tool and ecosystem perspective. The is one… Read More


Machine Learning for EDA – Inside, Outside and Everywhere Else

Machine Learning for EDA – Inside, Outside and Everywhere Else
by Mike Gianfagna on 03-18-2020 at 6:00 am

Paul Cunningham

Artificial intelligence (AI) is everywhere. The rise of the machines is upon us in case you haven’t noticed. Machine learning (ML) and its associated inference abilities promise to revolutionize everything from driving your car to making breakfast. We hear a lot about the macro, end-product impact of this technology, but there… Read More


5G SoCs Demand New Verification Approaches

5G SoCs Demand New Verification Approaches
by Mike Gianfagna on 03-16-2020 at 10:00 am

Simplified 4G network

Lately, I’ve been cataloging the number of impossible-to-verify technologies we face. All forms of machine learning and inference applications fall into this category. I’ve yet to see a regression test to prove a chip for an autonomous driving system will do the right thing in all cases. Training data bias is another interesting… Read More


Turbo-Charge Your Next PCIe SoC with PLDA Switch IP

Turbo-Charge Your Next PCIe SoC with PLDA Switch IP
by Mike Gianfagna on 03-12-2020 at 6:00 am

Integrated NVMe interfaces

SemiWiki has a new IP partner, PLDA and they bring a lot to the party.  Peripheral component interconnect express (PCIe) is a popular high-performance data interface standard. Think GPUs, RAID cards, WiFi cards or solid-state disk (SSD) drives connected to a motherboard. The protocol offers much higher throughput than previous… Read More


Achieving Design Robustness in Signoff for Advanced Node Digital Designs

Achieving Design Robustness in Signoff for Advanced Node Digital Designs
by Mike Gianfagna on 03-09-2020 at 10:00 am

Synopsys SemiWiki STARRC Webinar 1

I had the opportunity to preview an upcoming webinar on SemiWiki that deals with design robustness for signoff regarding advanced node digital designs (think single-digit nanometers). “Design robustness” is a key term – it refers to high quality, high yielding SoCs that come up quickly and reliably in the target system. We all… Read More


Designing Next Generation Memory Interfaces: Modeling, Analysis, and Tips

Designing Next Generation Memory Interfaces: Modeling, Analysis, and Tips
by Mike Gianfagna on 03-04-2020 at 10:00 am

IBIS AMI vs. Transient

At DesignCon 2020, there was a presentation by Micron, Socionext and Cadence that discussed design challenges and strategies for using the new low-power DDR specification (LPDDR5). As is the case with many presentations at DesignCon, ecosystem collaboration was emphasized. Justin Butterfield (senior engineer at Micron)… Read More


GLOBALFOUNDRIES Sets a New Bar for Advanced Non-Volatile Memory Technology

GLOBALFOUNDRIES Sets a New Bar for Advanced Non-Volatile Memory Technology
by Mike Gianfagna on 03-02-2020 at 6:00 am

eNVM applications


Whether it’s the solid-state disk in your laptop, IoT/automotive hardware or  edge-based AI, embedded non-volatile memory (eNVM) is a critical building block for these and many other applications. The workhorse technology for this capability has typically been NOR flash (eFlash), but a problem looms as eFlash presents challenges… Read More


Navigating Memory Choices for Your Next Low-Power Design

Navigating Memory Choices for Your Next Low-Power Design
by Mike Gianfagna on 02-27-2020 at 10:00 am

Memory options

Choosing a memory architecture can be a daunting task. There are many options to choose from, each with their own power, performance, area and cost profile. The right choice can make a new design competitive and popular in the market. The wrong choice can doom the whole project to failure.

Vadhiraj Sankaranarayanan, senior technical… Read More