EDA on the iPad

EDA on the iPad
by Daniel Payne on 04-02-2012 at 1:16 pm

ss ipad

I started a forum discussion about running Schematic Capture and SPICE on an iPad back in January, since then I bought an iPad 3rd generation and tried out that app.

It was easy to visit the App store, find the Spicy Schematic Capture app, download and start learning how to use their schematic and SPICE circuit simulator.… Read More


IC Layout Design at Qualcomm

IC Layout Design at Qualcomm
by Daniel Payne on 03-31-2012 at 6:54 pm

I first met Betty Pokerwinski of Qualcomm at LinkedIn in the group called IC Layout Designers. I post frequently on LinkedIn and a blog article on an EDA tool called Visual Design Diff from ClioSoft created quite a discussion, enough so that I contacted Betty to learn more about her IC layout group at Qualcomm.

Questions and AnswersRead More


SOC Prototyping with FPGAs from a Smaller Vendor

SOC Prototyping with FPGAs from a Smaller Vendor
by Daniel Payne on 03-23-2012 at 10:43 am

The two large EDA companies offering SOC prototyping with FPGA-based boards are Synopsys and Cadence, however there’s a smaller vendor called Polaris Design Systems that also have a product in this important design verification category. I spoke on Wednesday with Rahm Shastry, CEO of Polaris to learn more about this company… Read More


What’s Up with SNUG This Year in Santa Clara?

What’s Up with SNUG This Year in Santa Clara?
by Daniel Payne on 03-22-2012 at 11:04 am

Next week is a big deal because it’s when Synopsys has their annual user group meeting, SNUG in Santa Clara at the Convention Center from Monday through Wednesday. I’d love to hear if they have made any decisions on the new product roadmap after the Magma acquisition, although it’s probably too early to tell.… Read More


A Chat with John Stabenow

A Chat with John Stabenow
by Daniel Payne on 03-20-2012 at 10:57 am

John Stabenow is the marketing group director at Cadence for the Virtuoso products and it has been awhile since we last talked, so we met for lunch on Friday at McMenamins in a city called West Linn, half-way between where we both live in Oregon. I had blogged about Interoperability at DAC 2010 and we had a public exchange at Chip Design… Read More


Timing Closure for ECOs in your SOC Design

Timing Closure for ECOs in your SOC Design
by Daniel Payne on 03-14-2012 at 1:07 pm

I decided to attend a webinar today hosted by Synopsys, “Streamline Your PrimeTime ECO Flow For Fastest Setup, Hold and Timing DRC Closure.” The format was to present slides first then hold for questions until the end. Enough time was spent on questions which made this webinar different than most other webinars I’ve… Read More


More Growth in EDA

More Growth in EDA
by Daniel Payne on 03-12-2012 at 6:53 pm

I love to read good news about growth in EDA especially when our industry has seen single-digit growth for several years now. What I read on March 8th from ClioSoft stated a 53% increase in bookings for 2011, now that’s what I call growth.

ClioSoft provides Hardware Configuration Management (HCM) software to EDA users typically… Read More


Book Review – iWoz

Book Review – iWoz
by Daniel Payne on 03-12-2012 at 11:01 am

I bought my first personal computer in 1979, it was a Radio Shack TRS-80 Model I with just 16KB of RAM, a BW monitor and casette tape for storage. The reason that I chose the Radio Shack over the Apple II was that it cost less, so I was always interested in Apple products and the engineers behind them since the early days. It was pure delight… Read More


IC Custom IP Blocks – EM and IR Drop Effects

IC Custom IP Blocks – EM and IR Drop Effects
by Daniel Payne on 03-06-2012 at 5:33 pm

Designing custom IP blocks is a challenge at the transistor-level and I wanted to learn what the recommended methodology and EDA tool flow was at Synopsys. They have a webinar that you can register for and it takes 30 minutes to learn what they have to say, or you can read a White Paper. If you cannot spare that much time, then my summary… Read More