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Gim Tan at Magma did a webinar on analog circuit optimization, so I watched it today to see what I could learn about their approach. Gim is a Staff AE, so not much marketing fluff to wade through in this webinar.
The old way of designing custom analog circuits involves many tedious and error prone iterations between front-end (Schematic… Read More
Smaller IC nodes bring new challenges to the art of IC layout for AMS designs, like Layout Dependent Effects (LDE). If your custom IC design flow looks like the diagram below then you’re in for many time-consuming iterations because where you place each transistor will impact the actual Vt and Idsat values, which are now a … Read More
My first IC design in 1978 was a 16Kb DRAM chip at Intel and our researchers discovered the strange failure of Soft Errors caused by Alpha particles in the packaging and neutron particles which are more prominent at higher altitudes like in Denver, Colorado. Before today if you wanted to know the Soft Error Rate (SER) you had to fabricate… Read More
This morning I attended a webinar about MEMS and IC co-design from a company called SoftMEMS along with Tanner EDA. I learned that you can co-design MEMS and IC either in a bottom-up or top-down methodology, and that this particular flow has import/export options to fit in with your mechanical simulation tools (Ansys, Comsol, Open… Read More
As a blogger I write weekly about the EDA industry and certainly our industry enables products like Smart Phones and Tablets to even exist, however if we really believed in these mobile devices then what should our web sites look like on a mobile device?
It’s a simple question, yet I first must define mobile-friendly before… Read More
I learned about MEMS layout automation at a webinar in December and plan to attend another webinar next week on April 10thwhere two companies have created a MEMS-IC co-design flow, Tanner EDA and SoftMEMS. The big challenge is to ensure that the MEMS and electronic parts of a new design will simulate correctly before committing … Read More
I started a forum discussion about running Schematic Capture and SPICE on an iPad back in January, since then I bought an iPad 3rd generation and tried out that app.
It was easy to visit the App store, find the Spicy Schematic Capture app, download and start learning how to use their schematic and SPICE circuit simulator.… Read More
I first met Betty Pokerwinski of Qualcomm at LinkedIn in the group called IC Layout Designers. I post frequently on LinkedIn and a blog article on an EDA tool called Visual Design Diff from ClioSoft created quite a discussion, enough so that I contacted Betty to learn more about her IC layout group at Qualcomm.
Questions and Answers… Read More
The two large EDA companies offering SOC prototyping with FPGA-based boards are Synopsys and Cadence, however there’s a smaller vendor called Polaris Design Systems that also have a product in this important design verification category. I spoke on Wednesday with Rahm Shastry, CEO of Polaris to learn more about this company… Read More
Next week is a big deal because it’s when Synopsys has their annual user group meeting, SNUG in Santa Clara at the Convention Center from Monday through Wednesday. I’d love to hear if they have made any decisions on the new product roadmap after the Magma acquisition, although it’s probably too early to tell.… Read More
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Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot