An FPGA Design Flow with Aldec Tools

An FPGA Design Flow with Aldec Tools
by Daniel Payne on 12-04-2012 at 12:19 pm

I’ve used FPGA vendor-supplied tools from both Xilinxand Lattice Semibefore, so I wanted to see what EDA tools Aldec has to offer for FPGA design. I read the Aldecwhite paper, Corporate Standardization of FPGA Design Flow, and summarize what I found.… Read More


Mixed-Signal Methodology Guide: Design Management

Mixed-Signal Methodology Guide: Design Management
by Daniel Payne on 12-04-2012 at 11:04 am

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I reviewed the book Mixed-Signal Methodology Guidein August of this year published by Cadence, and decided to follow up with one of the authors, Michael Henrie from ClioSoft, to learn more about the importance of Design Management for AMS. Michael is a Software Engineering Manager at ClioSoft and has worked at Zarlink Semi, Legerity,… Read More


Variation-Aware Design: A Hands-on Field Guide

Variation-Aware Design: A Hands-on Field Guide
by Daniel Payne on 12-01-2012 at 2:57 pm

IC designers using advanced nodes are acutely aware of how variation effects in the silicon itself are causing increased analysis and design efforts in order to yield chips at acceptable levels. Four authors from Solidoare so passionate about this topic that they combined their years of experience into a book that I had a chance… Read More


ASIC Prototyping: Dini Group and Tektronix

ASIC Prototyping: Dini Group and Tektronix
by Daniel Payne on 11-25-2012 at 7:00 pm

Collaboration in EDA is nothing new, however you may not be aware of how the Dini Group and Tektronix have worked together on an FPGA prototyping platform to address issues like debugging with full visibility across an entire multi-FPGA design. At SemiWiki we’ve blogged a couple of times so far about the new debug approach… Read More


Internet of Things, My Bluetooth Headset

Internet of Things, My Bluetooth Headset
by Daniel Payne on 11-20-2012 at 8:42 pm

A catchy phrase used by bloggers and journalists these days is “Internet of Things“, or IoT if you prefer acronyms. All of this is made possible by EDA tools in the hands of SoC designers to create useful products like my Jawbone ICON bluetooth headset. Tonight I discovered that I could customize my bluetooth headset… Read More


What I Learned About FPGA-based Prototyping

What I Learned About FPGA-based Prototyping
by Daniel Payne on 11-15-2012 at 8:10 pm

Today I attended an Aldec webinar about ASIC and SoC prototyping using the new HES-7 Board. This prototyping board is based on the latest Virtex-7 FPGA chips from Xilinx.

You can view the recorded webinar here, which takes about 30 minutes (should be available in a few days). I first blogged about the HES-7 two months ago, ASIC PrototypingRead More


Static Timing Analysis for Memory Characterization

Static Timing Analysis for Memory Characterization
by Daniel Payne on 11-11-2012 at 6:18 pm

Modern SoC (System On Chip) designs contain a larger number of RAM (Random Access Memory) instances, so how do you know what the speed, timing and power are for any instance? There are a couple of approaches:
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  • Trust the IP supplier to give you models that use polynomial equations to curve-fit the performance numbers based
  • Read More

    Chip On Wafer On Substrate (CoWoS)

    Chip On Wafer On Substrate (CoWoS)
    by Daniel Payne on 11-03-2012 at 5:19 pm

    tsmc cowos test vehicle1

    Our EDA industry loves three letter acronyms so credit the same industry for creating a five letter acronym CoWoS. Two weeks ago TSMC announced tape-out of their first CoWoS test chip integrating with JEDEC Wide I/O mobile DRAM interface, making me interested enough to read more about it. At the recent TSMC Open Innovation Platform… Read More