Static Low-Power Verification in Mixed-Signal SoC Designs

Static Low-Power Verification in Mixed-Signal SoC Designs
by Daniel Payne on 06-19-2013 at 2:02 pm

IC designer Shubhyant Chaturvediof AMD used EDA tools from Mentor Graphicsand Concept Engineeringto perform static, low-power verification of a mixed-signal SoC design with a combined CPU and GPU. Shubhyant presented a poster session at DAC two weeks ago in Austin, and I wanted to share it with my readers here at SemiWiki.… Read More


A New STA Tool at DAC, No Not Cadence

A New STA Tool at DAC, No Not Cadence
by Daniel Payne on 06-19-2013 at 12:15 pm

The big EDA companies get big attention at DAC, however sometimes the little EDA start-ups like Arcadia Innovationhave a new product that can be overlooked. On Tuesday at DAC I met with Joey Lin, founder of Arcadia Innovation and learned about his new STA (Static Timing Analysis) tool called TimeHawk .… Read More


Deploying 14nm FinFETs in your Next Mobile SoC

Deploying 14nm FinFETs in your Next Mobile SoC
by Daniel Payne on 06-19-2013 at 11:05 am

At DAC in Austin a design company, foundry and EDA vendor teamed up to present their experiences with 14nm FinFETs during a breakfast on Tuesday.

Panelists included:

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Tela Innovations, DAC Update

Tela Innovations, DAC Update
by Daniel Payne on 06-13-2013 at 12:16 pm

Lawsuits in EDA are common, and Tela Innovationsfiled a huge complaint back in February with the U.S. International Trade Commission (USITC) against HTC Corporation; HTC America, Inc.; LG Electronics, Inc.; LG Electronics U.S.A., Inc.; LG Electronics MobileComm U.S.A., Inc.; Motorola Mobility LLC; Nokia Corporation; Nokia,… Read More


GPU-Based SPICE Simulator for Library Characterization

GPU-Based SPICE Simulator for Library Characterization
by Daniel Payne on 06-13-2013 at 11:55 am

Jeff Tuanis the CEO and President of an EDA startup called G-Analog, founded in May 2012. His background includes working at: Cadence, Epic, Synopsys, Nassda, Chartered Semi and GLOBALFOUNDRIES. Jason Lu is the R&D manager. We met at DAC last week to talk about his company’s new product called Gchar for IC library characterization… Read More


Custom Physical IC Design update from Cadence

Custom Physical IC Design update from Cadence
by Daniel Payne on 06-10-2013 at 8:05 pm

Custom IC design and layout is becoming more difficult at 20nm and smaller nodes, so the EDA tools have to get smarter and work harder for us in order to maintain productivity with the fewest iterations to reach our specs. Dave Stylesand John Stabenow of Cadence met with me last Monday in Austin at the DAC exhibit area.


John StabenowRead More