On my first job out of college as an IC design engineer I was surprised to discover that a major cost of chips was in the amount of time spent on the tester before being shipped. That is still true today, so how would you keep your tester time down, test coverage high and with a minimum number of pins when using multiple processors on a single… Read More
Author: Daniel Payne
Best Practices for Using DRC, LVS and Parasitic Extraction – on YouTube
EDA companies produce a wealth of content to help IC engineers get the best out of their tools through several means:
- Reference Manuals
- User Guides
- Tutorials
- Workshops
- Seminars
- Training Classes
- Phone Support
- AE visits
Full Chip IR Drop Analysis using Distributed Multi Processing
IR drop analysis across your board, package and SoC ensures that your Power Delivery Network (PDN) is robust, and that your system will function to spec. There are both static and dynamic approaches to IR drop analysis of a full-chip with billions of transistors, while the dynamic approach produces the most accurate results compared… Read More
SoC Constraints, Design & Verification at DAC
I hadn’t followed EDA start-up company Ausdiamuch before, so at DAC I met with Sam Appleton, CEO to find out what they are all about.
Sanjay Lall, Sam Appleton – Ausdia
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Design Test and Regression Management of SoCs
Eric Peersfounded Missing Link tools in 2008 and his company was acquiredby Methodics in 2012, so I met with him at DAC to understand how their EDA tools for Design, Test and Regression Management are used in an SoC design.
Eric Peers, Methodics… Read More
Speeding Design Closure at DAC
At DAC you can measure buzz by how many people are crowded into your booth. I saw a crowd at the Oasys booth, so stopped to take in their 10 minute overview presentation. Here’s what I learned.… Read More
Analysis of Power, Thermal, EM, IR at DAC
Most EDA start-up companies have a narrow product focus to complement existing tool flows, however Invarian is taking a much bolder approach by offering tools for:
- Power analysis
- Thermal analysis
- EM / IR analysis
- 3D Thermal analysis
Analog FastSPICE at DAC
Berkeley DA coined the phrase “Analog FastSPICE”, and I’ve been getting an update from them at DAC for several years now. In Austin I met with Paul Estradathe COO and Patrick Muyshondt.
Paul Estrada
Paul Estrada, COO (circa 2010)
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HW Prototyping and HLS at DAC
I love it when EDA companies send their engineers to DAC because I learn more of the unvarnished truth about their products. I met with Bill Thomas of Aldec to get an update on their HW prototyping boards, then two NEC engineers to learn about High Level Synthesis.
HW Prototyping
Bill Thomas, Research Engineer at Aldec
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EDA Tools from China at DAC
Last year I was surprised at DAC by an un-heard of EDA company from China, ICScape. This year I followed up and spoke with Ravi Ravikumar about what’s new with ICScape in 2013.… Read More
Selling the Forges of the Future: U.S. Report Exposes China’s Reliance on Western Chip Tools