Windows on a TV

Windows on a TV
by Daniel Payne on 01-23-2015 at 12:00 am

This month I upgraded my TV at home with a 40″ LED set from Samsung, Denon AV receiver and Samsung Blu-ray player. Also being a Google fan I bought a Chromecast device.




At CES there were multiple announcements from Intel, and one that caught my eye was the Intel Compute Stick because it reminded me of the Google Chromecast device… Read More


Managing Semiconductor IP

Managing Semiconductor IP
by Daniel Payne on 01-21-2015 at 5:00 pm

SemiWiki blogger Eric Esteve does an excellent job writing about all of the semiconductor IP available, and the popularity of IP is only growing more each year. Here’s a projection from IBS about semiconductor IP showing revenues of $4.7B by 2020:

Analyst Gary Smith divides IP into three broad categories: Functional, Foundation… Read More


Not All RTL Synthesis Approaches are the Same

Not All RTL Synthesis Approaches are the Same
by Daniel Payne on 01-20-2015 at 7:00 pm

My first experience with logic synthesis was at Silicon Compilers in the late 1980s using a tool called Genesil. Process technology since that time has moved from 3 um down to 20 nm, so there are new challenges for RTL synthesis. Today you can find logic synthesis tools being offered by the big three in EDA: Synopsys, Cadence, MentorRead More


Verification of Wireless RFIC Designs

Verification of Wireless RFIC Designs
by Daniel Payne on 01-15-2015 at 1:30 pm

Wireless technology is all around as I use cellular on an Android phone, WiFi to connect my MacBook Pro to the internet, Bluetooth for a headset, ANT+ for my cycling computer, and NFC to speed up electronic payments on the Android phone. Here’s a big picture look at some of the modern wireless standards available to choose from:… Read More


Cycling, Semiconductors and CES 2015

Cycling, Semiconductors and CES 2015
by Daniel Payne on 01-06-2015 at 10:00 pm

I’m an avid cyclist that rode some 6,744.3 miles in 2014, according to www.strava.com, a free web site and popular app for road bikers like me. At CES this week I’ve read about many creative devices and apps to make your cycling experience better, so here’s my take on all of it.… Read More


WLAN Design Optimization at Lantiq

WLAN Design Optimization at Lantiq
by Daniel Payne on 01-02-2015 at 7:00 am

Right now I’m typing on my MacBook Pro computer connected to the Internet through WiFi, thanks to the electronics in both my laptop and WiFi router. I kind of take WiFi for granted because it is so ubiquitous throughout my daily life, yet there are IC designers at companies like Lantiq Semiconductorthat have to design and optimize… Read More


Methodology Help for Analog IC Designers

Methodology Help for Analog IC Designers
by Daniel Payne on 12-25-2014 at 7:00 am

Digital designers are more numerous than analog IC designers, and so they tend to get more attention from EDA vendors in terms of tools and automation methodologies. For an analog design team with specialists focused separately on schematics and layout there are several methodology questions that need to be addressed, like:… Read More


An Approach to Top-Down SoC Verification

An Approach to Top-Down SoC Verification
by Daniel Payne on 12-19-2014 at 1:00 pm

We’ve blogged dozens of times about UVM– Universal Verification Methodology at SemiWiki, and all of the major EDA vendors support UVM, so you may be lulled into thinking that UVM is totally adequate for top-down SoC verification. Yesterday I had a phone discussion with Frank Schirrmeister of Cadence about a new approach… Read More


How are the IoT and ESL Related?

How are the IoT and ESL Related?
by Daniel Payne on 12-16-2014 at 2:00 pm

A recent comment by a DACattendee mentioned that the IoT acronym was so over-used as to make him get upset at EDA vendors that all purport to be enabling the growing IoT revolution. One of the most common requirements that I hear about IoT electronics is that the power needs to be well understood and controlled during the design exploration… Read More


Benefits of Using Schematic Driven Layout

Benefits of Using Schematic Driven Layout
by Daniel Payne on 12-12-2014 at 12:00 pm

Most IC designs are developed by a team of professionals, often separated into distinct groups like front-end and back-end, logical and physical designers. Circuit designers use tools like schematic capture at the transistor-level to create a topology, then begin simulating the netlist with a SPICE simulator. Layout designers… Read More