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Rock music, invitation only tickets, hollywood lighting, journalists from around the world, live streaming on the web, yes, another typical Apple-orchestrated product launch on Monday, March 9th at the Yerba Buena Center in California.
Up first was a video about Apple’s store opening in West Lake China with superb cinematography.… Read More
Paul McLellan wrote about how he stumbled into blogging and it inspired me to share my story as well. I grew up in Minnesota and attended the U of Minnesota earning a bachelor’s degree in Electrical Engineering so that I could design computer chips. After interviewing in 1978 with HP, IBM, Intel and Motorola I decided to join… Read More
Your latest SoC has just begun the tape-out process and then marketing comes back with a small update to the specification to make your design more competitive, or maybe your regression tests just found a minor bug in a single IP block that needs to be fixed. Should you go back in your design flow, change the RTL source code and then completely… Read More
High Level Synthesis (HLS) tools have been around for at least two decades now, and you may recall that about one year ago Cadence acquired Forte. The whole promise of HLS is to provide more design and verification productivity by raising the design abstraction from RTL code up to SystemC, C or C++ code. With any acquisition it is natural… Read More
Our household members own both Apple and Android devices, so we wanted a way to share our photos or videos on the Samsung TV. The device we ended up buying is called Chromecast from Google, and it’s a small media streaming device that plugs into an HDMI port on our TV. We’ve had Chromecast for about six weeks now.… Read More
I got really involved in testability back at CrossCheck in the 1990’s when they designed a way for Gate Arrays to have 100% observability without any Design For Test (DFT) requirements on designers. The Japanese Gate Array companies loved this approach and their customers enjoyed the highest test coverage without being… Read More
One challenge in SoC projects is maintaining consistency between the specification, design and documentation throughout the product lifecycle. Imagine the chaos if your specification for power is 300 mW, the design is actually 350 mW and the documentation promises 250 mW. Traditionally the design and documentation process… Read More
My old headphones with microphone lost a channel, so it was time to upgrade and I went shopping for something that had high fidelity and fit over my ears, instead of on my ears. After some online research I opted for the Bose headphones, because that brand has been around for decades, they offer many models to choose from, and are readily… Read More
When I hear the phrase Static Timing Analysis (STA) the first EDA tool that comes to mind is PrimeTimefrom Synopsys, and this type of tool is essential to reaching timing closure for digital designs by identifying paths that are limiting chip performance. Sunil Walia, PrimeTime ADV marketing lead spoke with me by phone on Thursday… Read More
When chip designers moved from a gate-level design methodology to coding with RTL there was a learning curve involved, and the same thing happens when you move from RTL to High Level Synthesis (HLS) using C++ or SystemC coding. One great shortcut to this learning curve is the use of pre-defined library functions. I just heard about… Read More
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Facing the Quantum Nature of EUV Lithography