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Shorten the Learning Curve for High Level Synthesis

Shorten the Learning Curve for High Level Synthesis
by Daniel Payne on 01-27-2015 at 4:30 pm

When chip designers moved from a gate-level design methodology to coding with RTL there was a learning curve involved, and the same thing happens when you move from RTL to High Level Synthesis (HLS) using C++ or SystemC coding. One great shortcut to this learning curve is the use of pre-defined library functions. I just heard about a new library of 1D signal processing hardware ready to use in an HLS flow from Calypto:

Related – HLS: Major Improvement through Generations

The library is called CatWareand you get a set of filter and FFT models that can be customized with parameters and then synthesized using the Catapult tool. Some designers prefer to use C++, while others are attracted to SystemC, either way the CatWare libraries support both languages. You add these library models to your C++ or SystemC source code, and then set the parameters, like:

  • Input precision
  • Output precision
  • Number of stages
  • Number of taps
  • Architecture

During synthesis with Catapult is where you constrain the design to use a specific technology and define the clock frequency. Because you are receiving the source code for each library, you can even change it to better meet your needs or create derivatives.

Related – HLS Tools Coming into Limelight!

Each of the CatWare models has been run through a set of regression tests, so you’ve got something that has been verified in Simulink, C++ and RTL simulations already. Two extra verification techniques are also used: assertion synthesis and SLEC C property checking, helping to verify consistent behavior through synthesis.

Here’s what you get in the FFT library:

[TABLE] style=”width: 100%”
|-
| Catware FFT Blocks
| Radix 2 Fixed Point DIT
|
| Radix 2 Fixed Point
DIF

|
| Radix 2^2 Fixed
Point DIF

| Mix Radix Fixed Point
(2 and 2^2) DIF

| Configurable
Radix Fixed Point DIF

|-
| Supported Architectures
| Single Delay
Feed-back
| In Place
| Single Delay
Feed-back
| In Place
| Single Delay
Feed-back
| Single Delay
Feed-back
| In Place
|-
| Synthesizable C++ Model
| √
| √
| √
| √
| √
| √
| √
|-
| Synthesizable SystemC Model
| √
| √
| √
| √
| √
| √
| √
|-
| Simulink Model
| √
| √
| √
| √
| √
| √
| √
|-
| Configurable Bit Precision
| √
| √
| √
| √
| √
| √
| √
|-
| Configurable Stage-wise Scaling
| √
| √
| √
| √
| √
| √
| √
|-
| Configurable FFT Point
| √
| √
| √
| √
| √
| √
| √
|-
| Streaming Interfaces
| √
| √
| √
| √
| √
| √
| √
|-
| Configurable Delay Buffer Impl.
(Register/Memory)
| √
| NA
| √
| NA
| √
| √
| NA
|-
| Constant Twiddle Implementation
| √
| √
| √
| √
| √
| √
| √
|-
| Configurable Radix
| NA
| NA
| NA
| NA
| NA
| NA
| √
|-
| Option to Mix Radix
| NA
| NA
| NA
| NA
| NA
| NA
| √
|-
| Configurable Output Oder
(Natural or Bit-Reversed)
| X
| X
| X
| X
| X
| X
| √
|-
| C++ Interface Synthesis
| √
| √
| √
| √
| √
| √
| √
|-
| Multiview IO – HLS/TLM
| √
| √
| √
| √
| √
| √
| √
|-

Related – Designing Hardware with C++ and its Advantages

For filters, the CatWare library has:
[TABLE] style=”width: 100%”
|-
| Catware Filter Blocks
| FIR Constant Coefficient
| FIR Programable
Coefficient

| FIR Loadable
Coefficient

| CIC Interpolator
& Decimator

| Moving
Avergage

| Integrate
& Dump

| Poly Phase Interpolator
& Decimator

|-
| Supported
Architectures
| Shift Register Circular
Buffer Rotational Shift
Folded – Even Taps
Folded – Odd Taps
Transpose
| Shift Register Circular
Buffer Rotational Shift
Folded – Even Taps
Folded – Odd Taps
Transpose
| Shift Register Circular
Buffer Rotational Shift
Folded – Even Taps
Folded – Odd Taps
Transpose
| Limited
Precision^
Full Precision
| 1D
Windowing
| NA
| NA
|-
| Synthesizable C++
Model
| √
| √
| √
| √
| √
| √
| √
|-
| Synthesizable SystemC
Model
| √
| √
| √
| √
| √
| √
| √
|-
| Simulink Model
| X
| X
| X
| √
| √
| X
| √
|-
| Multi-Channel Support
| X
| X
| X
| √
| X
| √
| X
|-
| Configurable Bit-Widths
| √
| √
| √
| √
| √
| √
| √
|-
| Configurable Rate
| NA
| NA
| NA
| √
| NA
| NA
| √
|-
| Configurable Number
of Taps
| √
| √
| √
| NA
| NA
| NA
| √
|-
| Streaming Interfaces
| √
| √
| √
| √
| √
| √
| √
|-
| Configurable Window
Type (Clip or Mirror)
| NA
| NA
| NA
| NA
| √
| NA
| NA
|-
| Configurable
Differential Delay
| NA
| NA
| NA
| √
| NA
| NA
| NA
|-
| C++ Interface Synthesis
| √
| √
| √
| √
| √
| √
| √
|-
| Multiview
IO – HLS/TLM
| √
| √
| √
| √
| √
| √
| √
|-

Summary

Give HLS a try on your next DSP design, and shorten your learning curve by using parameterized libraries for filters and FFT functions. This approach is sure to save you many days of engineering effort compared to starting from scratch.


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