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Wally Rhines is one of the most prolific speakers the semiconductor industry has ever experienced. Wally is also one of the most read bloggers on SemiWiki.com, sharing his life’s story which is captured in his first book: From Wild West to Modern Life the Semiconductor Evolution.
On April 2nd at 10am PDT we will host Wally on a live… Read More
If it’s your job to get a SoC design through synthesis, timing/power closure and final verification, the last thing you need are surprises in new versions of the IP blocks that are integrated into the design. If your IP supplier sends a new version, the best possible scenario is that this is only a small incremental change from… Read More
Before starting your next FPGA Prototyping Project you should catch the next SemiWiki webinar – “Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards”, in partnership with Aldec.
A significant portion of my 30+ years in the EDA industry has revolved around design verification with some form of FPGA … Read More
If you’ve spent any time at all in the semiconductor industry, you’ve heard the statement that verification consumes two-thirds or more of the total resources on a chip project. The estimates range up to 80%, in which case verification is taking four times the effort of the design process. The exact ratio is subject to debate, but… Read More
As a professional conference attendee I look for the most meaningful way to spend my time and workshops is one of the best. Especially when a customer is involved and there is no bigger EDA customer than Intel, absolutely.
System Level Flows for SoC Architecture Analysis and Design
Speakers:
Swaminathan Ramachandran – … Read More
Are you ready for the premier conference for functional design and verification of electronic systems?
Sponsored by Accellera Systems Initiative, DVCon is an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP)… Read More
In advanced technology nodes below 10nm, Design and Process Technology development have become increasingly intertwined. In older nodes the traditional technology roll-out was done mostly in a sequential manner with clear geometry scaling targets set by … Read More
The semiconductor industry lost another good one last week, my friend, co-worker, and longtime SemiWiki contributor, Randy Smith. Randy published sixty blogs on SemiWiki over the last eight years that have been viewed more than a half million times. That is quite a digital legacy, absolutely.
Like myself, and many other semiconductor… Read More
Howie began his career at Digital Equipment Corporation working on real-time device drivers, but within a few years started working at the other end of the stack with one of the pioneering electronic mail systems. Since then, Howie has worked on developing systems involving electronic mail, workflow processing, configuration… Read More
Now that the dust has settled and I’m out of cronovirus quarantine let’s talk about the Intel and AMD conference calls. Unfortunately, the Intel and AMD marketing teams are still outpacing engineering so it is difficult to write something serious but I will do my best.
Spoiler Alert: Both CEOs disappoint.
First an Intel 10nm update:… Read More
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Advancing Automotive Memory: Development of an 8nm 128Mb Embedded STT-MRAM with Sub-ppm Reliability