Why Synopsys’ Role in AMD’s Instinct MI455X Matters for AI Infrastructure

Why Synopsys’ Role in AMD’s Instinct MI455X Matters for AI Infrastructure
by Daniel Nenni on 10-27-2026 at 8:00 am

Conceptual Multi Die AI GPU Design

Synopsys’ collaboration with AMD on the Instinct MI455X GPU highlights a shift in how advanced AI processors are developed. Increasing performance depends on coordinating compute dies, memory interfaces, packaging, power delivery, and software. According to Synopsys’ announcement, AMD used its design, verification, … Read More


S2C Targets Faster RISC-V Bring-Up With Prototyping and AI

S2C Targets Faster RISC-V Bring-Up With Prototyping and AI
by Daniel Nenni on 10-27-2026 at 6:00 am

S2C advances RISC V FPGA development

S2C showcased FPGA prototyping and AI-assisted debugging at the sixth RISC-V Summit China, outlining how developers can validate complex processor designs and begin software development before first silicon. Its demonstrations connected three stages of that effort: running substantial RISC-V systems on FPGA hardware,… Read More


Accellera’s FSL 1.0 Gives Functional Safety Data a Common Language

Accellera’s FSL 1.0 Gives Functional Safety Data a Common Language
by Daniel Nenni on 10-26-2026 at 10:00 am

Interconnected functional safety across IP and systems

Accellera Systems Initiative has approved Functional Safety Language Standard 1.0 for release, addressing a persistent challenge in semiconductor development: moving safety information reliably between tools, engineering teams, and companies. Announced October 21, the standard establishes a common language and data… Read More


Inside the Package Powering Modern AI

Inside the Package Powering Modern AI
by Daniel Nenni on 10-26-2026 at 8:00 am

TSMC CoWoS is Critical to AI Chips

TSMC’s CoWoS-S is critical to the artificial intelligence era because it solves the central systems problem facing modern accelerators: computing capability is growing faster than conventional packages can supply data, power, and connectivity. CoWoS-S, meaning Chip-on-Wafer-on-Substrate with a silicon interposer, … Read More


CEO Interview with Eric Tsai of Mivium

CEO Interview with Eric Tsai of Mivium
by Daniel Nenni on 10-23-2026 at 11:00 am

Eric Tsai on the GaN starting material

Eric Tsai is Co-Founder and CEO of Mivium, Inc., a US-based materials technology company in Fremont, California developing submicron gallium nitride powder and related wide bandgap materials. He co-founded Mivium in 2022 after a career building and scaling consumer businesses, most recently as Vice President of Marketing… Read More


CEO Interview with Dr. Gleb Tsipursky of Disaster Avoidance Experts

CEO Interview with Dr. Gleb Tsipursky of Disaster Avoidance Experts
by Daniel Nenni on 10-23-2026 at 10:00 am

Human Centered AI Adoption at Work

Gleb Tsipursky, PhD, is the CEO and co-founder of Disaster Avoidance Experts, a consulting and training firm focused on helping organizations adopt AI through employee engagement and practical workflow redesign. He is a behavioral scientist and the author of The Psychology of AI Adoption at Work: From Resistance to Results… Read More


AJ Cooper is the Co-Founder and CEO of Itera

AJ Cooper is the Co-Founder and CEO of Itera
by Daniel Nenni on 10-23-2026 at 9:00 am

AJ Cooper Rewired in minutes

AJ Cooper is the Co-Founder and CEO of Itera, which developed the first-of-its-kind ‘fluid’ circuit board to make electronics physically programmable. Chips and software have been programmable for decades, but the interconnect between them has stayed fixed. By rewiring itself in real time, Itera’s board challenges

… Read More

Inside the Silicon: Analog Bits N2P2 Test Chip

Inside the Silicon: Analog Bits N2P2 Test Chip
by Daniel Nenni on 10-23-2026 at 9:00 am

Crimson Chip Precision

The future of intelligent computing depends on silicon that delivers more performance within tighter power and thermal limits. Combining TSMC’s advanced process technology with Analog Bits’ analog and mixed-signal expertise, we help designers address those demands through local power regulation, supply monitoring, precision… Read More


WEBINAR: Cut down EDA License cost by 25% with Stratos AI Nitro

WEBINAR: Cut down EDA License cost by 25% with Stratos AI Nitro
by Daniel Nenni on 10-23-2026 at 8:00 am

Smarter EDA Queues with Stratos AI

Expensive EDA licenses should keep chip design moving. Yet when license activity and job queues live in separate systems, teams can struggle to understand why work is waiting, which tools are underused, and whether additional spending will solve the problem. Idle seats, checkout failures, and stalled jobs can consume budgets… Read More


Executive Interview with Victor Lopez of RaiderChip

Executive Interview with Victor Lopez of RaiderChip
by Daniel Nenni on 10-23-2026 at 8:00 am

Generative AI at the Edge

Victor Lopez is Co-Founder and CTO at RaiderChip, with over 20 years of experience in FPGA and ASIC design. Throughout his career, he has led the development of semiconductor IP and custom hardware solutions licensed by international companies in sectors such as defense, aerospace, automotive and professional video, specializing… Read More