Axiomise Introduces nocProve to Transform NoC Design Verification

Axiomise Introduces nocProve to Transform NoC Design Verification
by Daniel Nenni on 03-12-2026 at 6:00 am

Axiomise Launches nocProve for NoC Verification

Axiomise has recently launched a new verification tool called nocProve which will transform how Network-on-Chip designs are validated in modern hardware development, absolutely.

The tool is designed to be the first configurable formal verification application specifically created for NoC implementations. It addresses… Read More


Advanced Architectures for Hybrid III-V/Silicon Quantum Cascade Lasers

Advanced Architectures for Hybrid III-V/Silicon Quantum Cascade Lasers
by Daniel Nenni on 03-10-2026 at 8:00 am

CAE INL 2025

Mid-infrared (MIR) photonic integrated circuits are emerging as a key technology for applications ranging from environmental monitoring and medical diagnostics to defense and industrial process control. The MIR spectral region, often referred to as the molecular “fingerprint” region, exhibits strong absorption features… Read More


Efficient Bump and TSV Planning for Multi-Die Chip Designs

Efficient Bump and TSV Planning for Multi-Die Chip Designs
by Daniel Nenni on 03-10-2026 at 6:00 am

Efficient Bump and TSV Planning for Multi Die Chip Designs

The semiconductor industry has experienced rapid advancements in recent years, particularly with the increasing demand for high-performance computing, artificial intelligence, and advanced automotive systems. Traditional single-die chip designs are often unable to meet modern PPA requirements. As a result, engineers… Read More


The Evolution of RISC-V and the Role of Andes Technology in Building a Global Ecosystem

The Evolution of RISC-V and the Role of Andes Technology in Building a Global Ecosystem
by Daniel Nenni on 03-09-2026 at 10:00 am

RISC V Now Andes Conference

During my frequent trips to Taiwan as a foundry relationship professional I remember meeting Frankwell Lin, CEO of Andes, in Taiwan 15+ years ago. As I walked to TSMC HQ from the Hotel Royal (my second home for many years) Andes was about mid point and Frankwell’s door was always open. Sometimes just tea, sometimes technology,… Read More


Capability Hardware Enhanced RISC Instructions CHERI Alliance

Capability Hardware Enhanced RISC Instructions CHERI Alliance
by Daniel Nenni on 03-09-2026 at 8:00 am

CHERI Alliance Overview 2026

The CHERI Alliance is a non-profit organization dedicated to accelerating the global adoption of CHERI (Capability Hardware Enhanced RISC Instructions), a technology designed to improve computer security at the hardware level. Established as an independent entity, the Alliance brings together industry leaders, researchers,… Read More


Keynote: On-Package Chiplet Innovations with UCIe

Keynote: On-Package Chiplet Innovations with UCIe
by Daniel Nenni on 03-08-2026 at 4:00 pm

Chiplet Summit Keynote UCIe 2026

In the rapidly evolving landscape of semiconductor technology, the Universal Chiplet Interconnect Express (UCIe) emerges as a groundbreaking open standard designed to revolutionize on-package chiplet integrations. Presented by Dr. Debendra Das Sharma, Chair of the UCIe Consortium and Intel Senior Fellow, at the ChipletRead More


CEO Interview with Jerome Paye of TAU Systems

CEO Interview with Jerome Paye of TAU Systems
by Daniel Nenni on 03-08-2026 at 2:00 pm

Jerome Paye CEO TAU Systems LR (1)

Jerome Paye has served as CEO of TAU Systems since late 2025, having joined the company shortly after its founding in 2022 as Chief Operating Officer. In that time, he has helped build TAU Systems into a high-performing team now focused on delivering the ultimate light source for semiconductor lithography.

Paye brings more than… Read More


Global 2nm Supply Crunch: TSMC Leads as Intel 18A, Samsung, and Rapidus Race to Compete

Global 2nm Supply Crunch: TSMC Leads as Intel 18A, Samsung, and Rapidus Race to Compete
by Daniel Nenni on 03-06-2026 at 6:00 am

TSMC 2NM Intel 18A Samsung 2nm Rapidus 2nm

The semiconductor industry is in the midst of a structural supply challenge that’s tightly coupled to exploding demand for advanced chips, especially those used in AI, HPC, and next-generation mobile and consumer devices. At the center of this vortex is the 2nm class of manufacturing technology, representing one of the most … Read More


From Satellites to 5G: Ceva’s PentaG-NTN™ Lowers Barriers for Terminal Innovators

From Satellites to 5G: Ceva’s PentaG-NTN™ Lowers Barriers for Terminal Innovators
by Daniel Nenni on 03-05-2026 at 8:00 am

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Ceva, Inc., a leading provider of silicon and software IP for the Smart Edge, has unveiled PentaG-NTN™, its groundbreaking 5G Advanced modem IP subsystem tailored for satellite user terminals in Low Earth Orbit (LEO) and Medium Earth Orbit (MEO) constellations. Announced at Mobile World Congress 2026 in Barcelona on March 3,… Read More


CHERI: Hardware-Enforced Capability Architecture for Systematic Memory Safety

CHERI: Hardware-Enforced Capability Architecture for Systematic Memory Safety
by Daniel Nenni on 03-03-2026 at 8:00 am

CHERI Technology Overview 2026

The rapid escalation of cyberattacks over the past two decades has exposed a fundamental weakness at the core of modern computing systems: the lack of memory safety. Industry data consistently shows that the majority of critical software vulnerabilities stem from memory corruption issues such as buffer overflows, use-after-free… Read More