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The GlobalFoundries DRC+ platform is one of the most innovative DFM technologies and was well represented at #48DAC. In case you missed it, here is a reprint of a DRC+ overview from GFI just prior to #48DAC:
DRC (Design Rule Constraints) are the fundamental principles in constraining VLSI (Very Large Scale Integration) circuit… Read More
GLOBALFOUNDRIES will show off its 28nm design ecosystem at #48DAC next week in San Diego. The company will feature a full design ecosystem for its 28nm High-k Metal Gate (HKMG) technology, including silicon-validated flows, process design kits (PDKs), design-for-manufacturing (DFM), and intellectual property (IP) in partnership… Read More
TSMC rolled out the new reference flows for 28nm design as part of the Open Innovation Platform. The biggest surprise (to me) is that Cadence is STILL in the TSMC reference flows!
The updated TSMC OIP wiki is here, the Reference Flow 12.0 wiki can be found here, the AMS 2.0 reference flow wiki is here, and the official TSMC PR is here. … Read More
The problem:To move a single lane variable data rate SerDes (serializer-deserializer) from a 65nm process to a 45nm process, achieving a maximum performance of up to 10.3 Gbps. This is a large piece of complex mixed-signal IP with handcrafted analog circuits. Circuit performance and robustness are critical and must be maintained… Read More
A three-dimensional integrated circuit (3D IC ) is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. The semiconductor industry is hotly pursuing this emerging technology in many different forms, as a result the full definition is still somewhat… Read More
The 48[SUP]th[/SUP] Design Automation Conference (DAC) is now upon us. DAC is billed as “the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions” for which I would have to agree with 100%.
The first DAC I attended was in 1984, Albuquerque New Mexico, which was one of the first to allow … Read More
A High-Definition Multimedia Interface (HDMI) IP core was being implemented in an advanced process technology. This fairly large and complex analog mixed-signal (AMS) IP comprising over 130K devices was close to being finalized and shipped to the customer. But many design rules at the foundry were unexpectedly changed from… Read More
Hard to believe a year has gone by since the big announcement of the Cadence Blueprint toBattle ‘Profitability Gap’; Counters Semiconductor Industry’s Greatest Threat! Having spent more time on it that I should have, here is my opinion on EDA360 on its first anniversary.
Richard Georing did a very nice anniversary piece “Ten Key… Read More
The corporate raiders are still throwing rocks at Mentor Graphics. I have followed this reality show VERY closely and find their latest assault seriously counterproductive. Disinformation is common in EDA but I expected more from Carl Icahn and the Raiderettes. They are quite the drama queens. Here is a billion dollar question:… Read More
TSMC continues to drive the economic recovery with impressive Q1 numbers and an even more impressive Q2 and Q3 outlook. TSMC is my economic bellwether due to its diverse customer base and shear volume of consumer electronics silicon. The big surprise in the 1 hour Q1 conference call is a new Giga Fab (#15) ground breaking this year… Read More
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RISC-V Virtualization and the Complexity of MMUs