In the 35 years since commercial EDA went mainstream a lot of advances have been made but the fundamental architecture and even the philosophy of tooling have really not advanced at all. Tools are designed around individual tasks – analysis and optimization within a specific domain – under the assumption that variability within… Read More
Author: Bernard Murphy
Google TPU Another Step in a Shifting Semiconductor Landscape
Markets work when consumers of a widget don’t feel there is significant differentiated value in making their own and would rather get lowest possible cost from experienced widget makers who can amortize their investment over high-volume sales to many customers. But that changes when a large consumer finds they can increase differentiated… Read More
DAC 2016 – Register Now
DAC is again going to be in Austin (reason enough to go), from June 6[SUP]th[/SUP]-8[SUP]th[/SUP] for the main event. A number of events caught my eye:
- Monday AM – custom hardware for algorithmic trading. If you want to know more about FinTech (technology for finance) this could be for you
- Another Monday morning session on Linux
Getting Low Power Design Right in Mixed Signal Designs
Mixed-signal design creates all sorts of interesting problems for implementation and verification flows, particularly when it comes to design for low power. We tend to think of mixed-signal as a few blocks like PLLs, ADCs and PHYs on the periphery of the design. Constrain and verify the digital power requirements up to analog … Read More
Deep Learning and Security
Deep learning based on neural nets is most commonly thought of as a very promising approach to scene recognition, text recognition and similar areas. Now there is increasing interest in applying this technology to security objectives. There were a number of papers on this topic in a 2015 BlackHat conference and there are several… Read More
Neural nets for Qualcomm Snapdragon
Neural nets are hot these days. In this forum certainly you can’t swing a cat without hitting multiple articles on the topic – I’ve written some myself. For me there are two reasons for this interest. First, neural nets are amazingly successful at what they do, for example in image recognition where they can beat… Read More
Ecosystem Partnership for Effective Network Hardware Design
When you’re designing a hardware solution to plug into what is arguably the most complex system of all – the Internet – you can’t get away with a little fake traffic to test whether your box is going to do all the right things at the right performance. You have to model realistic voice, video, data and wireless traffic in… Read More
Software-Driven Verification Drives Tight Links between Emulation and Prototyping
I’ve mentioned many times what has become a very common theme in SoC and system verification – it has to be driven by the software because any concept of exhaustively verifying “everything” is neither feasible nor meaningful. Emulation has become a critical component of this flow in validating and regressing… Read More
Metric-Driven Verification for System Signoff
Everyone knows that verification is hard and is consuming an increasing percentage of verification time and effort. And everyone should know that system-level verification (SoC plus at least some software and maybe models for other components on a board) is even harder—which is why you see hand-wringing over how incompletely… Read More
SpyGlass DFT ADV accelerates test closure – Xilinx and Synopsys webinar
Fed up with ECOing your way out of test problems? You might want to register for this webinar.When you’re building monster SoC FPGAs, you have all the same problems you have with any other SoC. That includes getting to very high test coverage as quickly as you can with a design targeted to the most advanced processes. We’re not just … Read More
More Headwinds – CHIPS Act Chop? – Chip Equip Re-Shore? Orders Canceled & Fab Delay